yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-25 11:27:00 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: add data cache invalidation cp15 instruction to cortex-r5

Browse source 
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.

Backports commit 95e9a242e2a393c7d4e5cc04340e39c3a9420f03 from qemu
This commit is contained in:
Luc MICHEL 2018-03-02 20:04:04 -05:00 committed by Lioncash
parent 565626ca63
commit 393019de26
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
qemu/target/arm/cpu.c
View file

@ -891,6 +891,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */
{ "ATCM", 15,9,1, 0,0,0, 0,ARM_CP_CONST, PL1_RW },
{ "BTCM", 15,9,1, 0,0,1, 0,ARM_CP_CONST, PL1_RW },
{ "DCACHE_INVAL", 15,15,5, 0,0,0, 0, ARM_CP_NOP, PL1_W },
REGINFO_SENTINEL
};