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target/arm: add data cache invalidation cp15 instruction to cortex-r5

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The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.

Backports commit 95e9a242e2a393c7d4e5cc04340e39c3a9420f03 from qemu
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Luc MICHEL 2018-03-02 20:04:04 -05:00 committed by Lioncash
parent 565626ca63
commit 393019de26
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1 changed files with 1 additions and 0 deletions
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qemu/target/arm/cpu.c
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@ -891,6 +891,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */ /* Dummy the TCM region regs for the moment */
{ "ATCM", 15,9,1, 0,0,0, 0,ARM_CP_CONST, PL1_RW }, { "ATCM", 15,9,1, 0,0,0, 0,ARM_CP_CONST, PL1_RW },
{ "BTCM", 15,9,1, 0,0,1, 0,ARM_CP_CONST, PL1_RW }, { "BTCM", 15,9,1, 0,0,1, 0,ARM_CP_CONST, PL1_RW },
{ "DCACHE_INVAL", 15,15,5, 0,0,0, 0, ARM_CP_NOP, PL1_W },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };