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arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

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This covers all the floating point convert operations.

Backports commit 2df581304193d70eaf0d22cf4cb4613f74b6e59b from qemu
This commit is contained in:
Alex Bennée 2018-03-08 18:24:36 -05:00 committed by Lioncash
parent d5f002b39a
commit 39a68548d1
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GPG key ID: 4E3C3CC1031BA9C7
6 changed files with 125 additions and 1 deletions
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2
qemu/aarch64.h
View file

@ -3729,6 +3729,8 @@
#define helper_advsimd_cgt_f16 helper_advsimd_cgt_f16_aarch64
#define helper_advsimd_div2h helper_advsimd_div2h_aarch64
#define helper_advsimd_divh helper_advsimd_divh_aarch64
#define helper_advsimd_f16tosinth helper_advsimd_f16tosinth_aarch64
#define helper_advsimd_f16touinth helper_advsimd_f16touinth_aarch64
#define helper_advsimd_max2h helper_advsimd_max2h_aarch64
#define helper_advsimd_maxh helper_advsimd_maxh_aarch64
#define helper_advsimd_maxnum2h helper_advsimd_maxnum2h_aarch64

2
qemu/aarch64eb.h
View file

@ -3729,6 +3729,8 @@
#define helper_advsimd_cgt_f16 helper_advsimd_cgt_f16_aarch64eb
#define helper_advsimd_div2h helper_advsimd_div2h_aarch64eb
#define helper_advsimd_divh helper_advsimd_divh_aarch64eb
#define helper_advsimd_f16tosinth helper_advsimd_f16tosinth_aarch64eb
#define helper_advsimd_f16touinth helper_advsimd_f16touinth_aarch64eb
#define helper_advsimd_max2h helper_advsimd_max2h_aarch64eb
#define helper_advsimd_maxh helper_advsimd_maxh_aarch64eb
#define helper_advsimd_maxnum2h helper_advsimd_maxnum2h_aarch64eb

2
qemu/header_gen.py
View file

@ -3749,6 +3749,8 @@ aarch64_symbols = (
'helper_advsimd_cgt_f16',
'helper_advsimd_div2h',
'helper_advsimd_divh',
'helper_advsimd_f16tosinth',
'helper_advsimd_f16touinth',
'helper_advsimd_max2h',
'helper_advsimd_maxh',
'helper_advsimd_maxnum2h',

32
qemu/target/arm/helper-a64.c
View file

@ -813,3 +813,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
return ret;
}
/*
* Half-precision floating point conversion functions
*
* There are a multitude of conversion functions with various
* different rounding modes. This is dealt with by the calling code
* setting the mode appropriately before calling the helper.
*/
uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
{
float_status *fpst = fpstp;
/* Invalid if we are passed a NaN */
if (float16_is_any_nan(a)) {
float_raise(float_flag_invalid, fpst);
return 0;
}
return float16_to_int16(a, fpst);
}
uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
{
float_status *fpst = fpstp;
/* Invalid if we are passed a NaN */
if (float16_is_any_nan(a)) {
float_raise(float_flag_invalid, fpst);
return 0;
}
return float16_to_uint16(a, fpst);
}

3
qemu/target/arm/helper-a64.h
View file

@ -73,3 +73,6 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)

85
qemu/target/arm/translate-a64.c
View file

@ -11397,6 +11397,46 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
only_in_vector = true;
/* current rounding mode */
break;
case 0x1a: /* FCVTNS */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x1b: /* FCVTMS */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x1c: /* FCVTAS */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x3a: /* FCVTPS */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x3b: /* FCVTZS */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x5a: /* FCVTNU */
need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x5b: /* FCVTMU */
need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x5c: /* FCVTAU */
need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x7a: /* FCVTPU */
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x7b: /* FCVTZU */
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@ -11429,7 +11469,36 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (is_scalar) {
/* no operations yet */
TCGv_i32 tcg_op = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
switch (fpop) {
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
default:
g_assert_not_reached();
}
/* limit any sign extension going on */
tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0xffff);
write_fp_sreg(s, rd, tcg_res);
tcg_temp_free_i32(tcg_ctx, tcg_res);
tcg_temp_free_i32(tcg_ctx, tcg_op);
} else {
for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32(tcg_ctx);
@ -11438,6 +11507,20 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
switch (fpop) {
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */