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target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}

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We will shortly use these to test for VFPv2 and VFPv3
in different situations.

Backports commit f67957e17cbf8fc3cc5d1146a2db2023404578b0 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 23:17:17 -04:00 committed by Lioncash
parent f73b360f8e
commit 39c49f488b
1 changed files with 18 additions and 0 deletions
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18
qemu/target/arm/cpu.h
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@ -3343,12 +3343,30 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports single precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
}
static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
{
/* Return true if CPU supports single precision floating point, VFPv3 */
return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
}
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv3 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
}
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so