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target-sparc: Store mmu index in TB flags

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Doing this instead of saving the raw PS_PRIV and TL. This means
that all nucleus mode TBs (TL > 0) can be shared. This fixes a
bug in that we didn't include HS_PRIV in the TB flags, and so could
produce incorrect TB matches for hypervisor state.

The LSU and DMMU states were unused by the translator. Including
them in TB flags meant unnecessary mismatches from tb_find_fast.

Backports commit 99a230638a3674e921224dbe628159c867d734b1 from qemu
This commit is contained in:
Richard Henderson 2018-02-25 04:51:43 -05:00 committed by Lioncash
parent 395e00cdc5
commit 39d1657fc3
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 13 additions and 15 deletions
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26
qemu/target-sparc/cpu.h
View file

@ -724,34 +724,32 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
trap_state* cpu_tsptr(CPUSPARCState* env);
#endif
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
#define TB_FLAG_MMU_MASK 7
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags;
*pc = env->pc;
*cs_base = env->npc;
flags = cpu_mmu_index(env, false);
#ifdef TARGET_SPARC64
// AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
*flags = (env->pstate & PS_PRIV) /* 2 */
| ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
| ((env->tl & 0xff) << 8)
| (env->dmmu.mmu_primary_context << 16); /* 16... */
if (env->pstate & PS_AM) {
*flags |= TB_FLAG_AM_ENABLED;
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
if ((env->def->features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
*flags |= TB_FLAG_FPU_ENABLED;
flags |= TB_FLAG_FPU_ENABLED;
}
#else
// FPU enable . Supervisor
*flags = env->psrs;
if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
*flags |= TB_FLAG_FPU_ENABLED;
flags |= TB_FLAG_FPU_ENABLED;
}
#endif
*pflags = flags;
}
static inline bool tb_fpu_enabled(int tb_flags)

2
qemu/target-sparc/translate.c
View file

@ -5402,7 +5402,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = cpu_mmu_index(env, false);
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);