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target/riscv: Convert RVXM insns to decodetree

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Backports commit d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 from qemu
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Bastian Koppelmann 2019-03-18 16:19:50 -04:00 committed by Lioncash
parent 4ea449a809
commit 3a5da0b939
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 17 additions and 9 deletions
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10
qemu/target/riscv/insn32.decode
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@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
mulhu 0000001 ..... ..... 011 ..... 0110011 @r
div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r

16
qemu/target/riscv/translate.c
View file

@ -1911,11 +1911,18 @@ static void decode_RV32_64C(DisasContext *ctx)
EX_SH(1) EX_SH(1)
EX_SH(12) EX_SH(12)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
return false; \
} \
} while (0)
bool decode_insn32(DisasContext *ctx, uint32_t insn); bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */ /* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c" #include "decode_insn32.inc.c"
/* Include insn module translation function */ /* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(DisasContext *ctx) static void decode_RV32_64G(DisasContext *ctx)
{ {
@ -1937,15 +1944,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode); imm = GET_IMM(ctx->opcode);
switch (op) { switch (op) {
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
#endif
if (rd == 0) {
break; /* NOP */
}
gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FP_LOAD: case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break; break;