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target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1

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MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.

Backports commit 86efbfb619a42061ac6439c074cfbf52df2ef2c2 from qemu
This commit is contained in:
Fredrik Noring 2018-11-23 18:28:45 -05:00 committed by Lioncash
parent 578172212f
commit 3d637206bd
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 42 additions and 11 deletions
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53
qemu/target/mips/translate.c
View file

@ -4407,6 +4407,44 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(tcg_ctx, t1);
}
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (reg == 0 && (opc == TX79_MMI_MFHI1 || opc == TX79_MMI_MFLO1)) {
/* Treat as NOP. */
return;
}
switch (opc) {
case TX79_MMI_MFHI1:
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg], tcg_ctx->cpu_HI[1]);
break;
case TX79_MMI_MFLO1:
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg], tcg_ctx->cpu_LO[1]);
break;
case TX79_MMI_MTHI1:
if (reg != 0) {
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_HI[1], tcg_ctx->cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_HI[1], 0);
}
break;
case TX79_MMI_MTLO1:
if (reg != 0) {
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_LO[1], tcg_ctx->cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_LO[1], 0);
}
break;
default:
MIPS_INVAL("mfthilo1 TX79");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
{
@ -4415,21 +4453,17 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
TCGv *cpu_HI = tcg_ctx->cpu_HI;
TCGv *cpu_LO = tcg_ctx->cpu_LO;
if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 ||
opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) {
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
return;
}
if (acc != 0) {
if (!(ctx->insn_flags & INSN_R5900)) {
check_dsp(ctx);
}
check_dsp(ctx);
}
switch (opc) {
case OPC_MFHI:
case TX79_MMI_MFHI1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(tcg_ctx, cpu_gpr[reg], cpu_HI[acc]);
@ -4440,7 +4474,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MFLO:
case TX79_MMI_MFLO1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(tcg_ctx, cpu_gpr[reg], cpu_LO[acc]);
@ -4451,7 +4484,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTHI:
case TX79_MMI_MTHI1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@ -4466,7 +4498,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTLO:
case TX79_MMI_MTLO1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@ -26659,11 +26690,11 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
break;
case TX79_MMI_MTLO1:
case TX79_MMI_MTHI1:
gen_HILO(ctx, opc, 1, rs);
gen_HILO1_tx79(ctx, opc, rs);
break;
case TX79_MMI_MFLO1:
case TX79_MMI_MFHI1:
gen_HILO(ctx, opc, 1, rd);
gen_HILO1_tx79(ctx, opc, rd);
break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */