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target-mips: enable XPA and LPA features

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Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.

Backports commit 6773f9b687e0a8ab4b638ef88d075fb233fb7669 from qemu
This commit is contained in:
Leon Alrae 2018-02-13 14:13:53 -05:00 committed by Lioncash
parent aff700ae6d
commit 3d72ec65bd
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 9 additions and 7 deletions
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16
qemu/target-mips/translate_init.c
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@ -500,10 +500,10 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP),
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | (1 << CP0C3_LPA),
MIPS_CONFIG4 | (1U << CP0C4_M),
0,
MIPS_CONFIG5 | (1 << CP0C5_UFR),
MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) | (1 << CP0C5_MVH),
(0 << CP0C5_M) | (1 << CP0C5_K) |
(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
@ -522,8 +522,9 @@ static const mips_def_t mips_defs[] =
(0x93 << FCR0_PRID),
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
40,
0,0, 0,0, 0,0, 0,0, 0,0,
(1 << CP0PG_ELPA), 0,
CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
MMU_TYPE_R4000,
},
@ -731,7 +732,8 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) |
(1U << CP0C3_M),
MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1 << CP0C4_M),
0,
@ -751,11 +753,11 @@ static const mips_def_t mips_defs[] =
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
42,
36,
48,
0,0, 0,0, 0,0, 0,0, 0,0,
(1 << CP0PG_ELPA),
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1U << CP0PG_RIE),
0,
CPU_MIPS64R6,
MMU_TYPE_R4000,
},