target/arm: Implement new VFP fp16 insn VINS

The fp16 extension includes a new instruction VINS, which copies the
lower 16 bits of a 32-bit source VFP register into the upper 16 bits
of the destination. Implement it.

Backports commit e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e

qemu/target/arm/translate-vfp.inc.c

@@ -3515,3 +3515,32 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
 
     return false;
 }
+
+static bool trans_VINS(DisasContext *s, arg_VINS *a)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    TCGv_i32 rd, rm;
+
+    if (!dc_isar_feature(aa32_fp16_arith, s)) {
+        return false;
+    }
+
+    if (s->vec_len != 0 || s->vec_stride != 0) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /* Insert low half of Vm into high half of Vd */
+    rm = tcg_temp_new_i32(tcg_ctx);
+    rd = tcg_temp_new_i32(tcg_ctx);
+    neon_load_reg32(s, rm, a->vm);
+    neon_load_reg32(s, rd, a->vd);
+    tcg_gen_deposit_i32(tcg_ctx, rd, rd, rm, 16, 16);
+    neon_store_reg32(s, rd, a->vd);
+    tcg_temp_free_i32(tcg_ctx, rm);
+    tcg_temp_free_i32(tcg_ctx, rd);
+    return true;
+}

qemu/target/arm/vfp-uncond.decode

@@ -74,3 +74,6 @@ VCVT        1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
             vm=%vm_sp vd=%vd_sp sz=2
 VCVT        1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
             vm=%vm_dp vd=%vd_sp sz=3
+
+VINS        1111 1110 1.11 0000 .... 1010 11 . 0 .... \
+            vd=%vd_sp vm=%vm_sp