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tcg-mips: Adjust prologue for mips64

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Take stack frame parameters out from the function body.

Backports commit 0973b1cff8b66f3561befb1f467b2ab4d1a7d55a from qemu
This commit is contained in:
Jin Guojie 2018-03-01 12:51:35 -05:00 committed by Lioncash
parent b55b7403a8
commit 3de761976c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 25 additions and 29 deletions
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54
qemu/tcg/mips/tcg-target.inc.c
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@ -739,16 +739,6 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false; return false;
} }
static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
{
if (val == (int16_t)val) {
tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val);
} else {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, val);
tcg_out_opc_reg(s, OPC_ADDU, reg, reg, TCG_TMP0);
}
}
/* Bit 0 set if inversion required; bit 1 set if swapping required. */ /* Bit 0 set if inversion required; bit 1 set if swapping required. */
#define MIPS_CMP_INV 1 #define MIPS_CMP_INV 1
#define MIPS_CMP_SWAP 2 #define MIPS_CMP_SWAP 2
@ -2286,42 +2276,48 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
return s->code_ptr; return s->code_ptr;
} }
/* Stack frame parameters. */
#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ TCG_TARGET_STACK_ALIGN - 1) \
& -TCG_TARGET_STACK_ALIGN)
#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
/* We're expecting to be able to use an immediate for frame allocation. */
QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
/* Generate global QEMU prologue and epilogue code */ /* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_qemu_prologue(TCGContext *s)
{ {
int i, frame_size; int i;
/* reserve some stack space, also for TCG temps. */ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
frame_size = ARRAY_SIZE(tcg_target_callee_save_regs) * 4
+ TCG_STATIC_CALL_ARGS_SIZE
+ CPU_TEMP_BUF_NLONGS * sizeof(long);
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
~(TCG_TARGET_STACK_ALIGN - 1);
tcg_set_frame(s, TCG_REG_SP, ARRAY_SIZE(tcg_target_callee_save_regs) * 4
+ TCG_STATIC_CALL_ARGS_SIZE,
CPU_TEMP_BUF_NLONGS * sizeof(long));
/* TB prologue */ /* TB prologue */
tcg_out_addi(s, TCG_REG_SP, -frame_size); tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) { for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
tcg_out_st(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i], tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4); TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
} }
/* Call generated code */ /* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tb_ret_addr = s->code_ptr;
/* TB epilogue */ /* TB epilogue */
for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) { tb_ret_addr = s->code_ptr;
tcg_out_ld(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i], for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4); tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
} }
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
/* delay slot */ /* delay slot */
tcg_out_addi(s, TCG_REG_SP, frame_size); tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
if (use_mips32r2_instructions) { if (use_mips32r2_instructions) {
return; return;