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tcg-mips: Adjust prologue for mips64
Take stack frame parameters out from the function body. Backports commit 0973b1cff8b66f3561befb1f467b2ab4d1a7d55a from qemu
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b55b7403a8
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3de761976c
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@ -739,16 +739,6 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
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return false;
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return false;
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}
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}
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static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
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{
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if (val == (int16_t)val) {
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tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, val);
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tcg_out_opc_reg(s, OPC_ADDU, reg, reg, TCG_TMP0);
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}
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}
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/* Bit 0 set if inversion required; bit 1 set if swapping required. */
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/* Bit 0 set if inversion required; bit 1 set if swapping required. */
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#define MIPS_CMP_INV 1
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#define MIPS_CMP_INV 1
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#define MIPS_CMP_SWAP 2
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#define MIPS_CMP_SWAP 2
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@ -2286,42 +2276,48 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
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return s->code_ptr;
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return s->code_ptr;
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}
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}
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/* Stack frame parameters. */
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#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
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#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
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#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
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#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
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+ TCG_TARGET_STACK_ALIGN - 1) \
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& -TCG_TARGET_STACK_ALIGN)
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#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
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/* We're expecting to be able to use an immediate for frame allocation. */
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QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
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/* Generate global QEMU prologue and epilogue code */
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/* Generate global QEMU prologue and epilogue code */
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static void tcg_target_qemu_prologue(TCGContext *s)
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static void tcg_target_qemu_prologue(TCGContext *s)
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{
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{
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int i, frame_size;
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int i;
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/* reserve some stack space, also for TCG temps. */
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tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
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frame_size = ARRAY_SIZE(tcg_target_callee_save_regs) * 4
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+ TCG_STATIC_CALL_ARGS_SIZE
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+ CPU_TEMP_BUF_NLONGS * sizeof(long);
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frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
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~(TCG_TARGET_STACK_ALIGN - 1);
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tcg_set_frame(s, TCG_REG_SP, ARRAY_SIZE(tcg_target_callee_save_regs) * 4
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+ TCG_STATIC_CALL_ARGS_SIZE,
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CPU_TEMP_BUF_NLONGS * sizeof(long));
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/* TB prologue */
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/* TB prologue */
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tcg_out_addi(s, TCG_REG_SP, -frame_size);
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
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for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
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for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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tcg_out_st(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
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tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
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TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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}
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/* Call generated code */
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/* Call generated code */
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tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
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tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
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/* delay slot */
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tb_ret_addr = s->code_ptr;
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/* TB epilogue */
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/* TB epilogue */
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for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
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tb_ret_addr = s->code_ptr;
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tcg_out_ld(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
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for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
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tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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}
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tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
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tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
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/* delay slot */
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/* delay slot */
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tcg_out_addi(s, TCG_REG_SP, frame_size);
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
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if (use_mips32r2_instructions) {
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if (use_mips32r2_instructions) {
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return;
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return;
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