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tcg/s390: Merge ori+xori facilities check to tcg_target_op_def

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Backports commit e42349cbd6afd1f6838e719184e3d07190c02de7 from qemu
This commit is contained in:
Richard Henderson 2018-03-04 13:36:18 -05:00 committed by Lioncash
parent becadbe755
commit 3df9d84459
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 33 additions and 68 deletions
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101
qemu/tcg/s390/tcg-target.inc.c
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@ -40,8 +40,8 @@
#define TCG_CT_CONST_S16 0x100
#define TCG_CT_CONST_S32 0x200
#define TCG_CT_CONST_ORI 0x400
#define TCG_CT_CONST_XORI 0x800
#define TCG_CT_CONST_NN16 0x400
#define TCG_CT_CONST_NN32 0x800
#define TCG_CT_CONST_U31 0x1000
#define TCG_CT_CONST_S33 0x2000
#define TCG_CT_CONST_ZERO 0x4000
@ -401,11 +401,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'J':
ct->ct |= TCG_CT_CONST_S32;
break;
case 'O':
ct->ct |= TCG_CT_CONST_ORI;
case 'N':
ct->ct |= TCG_CT_CONST_NN16;
break;
case 'X':
ct->ct |= TCG_CT_CONST_XORI;
case 'M':
ct->ct |= TCG_CT_CONST_NN32;
break;
case 'C':
/* ??? We have no insight here into whether the comparison is
@ -430,60 +430,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
return ct_str;
}
/* Immediates to be used with logical OR. This is an optimization only,
since a full 64-bit immediate OR can always be performed with 4 sequential
OI[LH][LH] instructions. What we're looking for is immediates that we
can load efficiently, and the immediate load plus the reg-reg OR is
smaller than the sequential OI's. */
static int tcg_match_ori(TCGType type, tcg_target_long val)
{
if (s390_facilities & FACILITY_EXT_IMM) {
if (type == TCG_TYPE_I32) {
/* All 32-bit ORs can be performed with 1 48-bit insn. */
return 1;
}
}
/* Look for negative values. These are best to load with LGHI. */
if (val < 0) {
if (val == (int16_t)val) {
return 0;
}
if (s390_facilities & FACILITY_EXT_IMM) {
if (val == (int32_t)val) {
return 0;
}
}
}
return 1;
}
/* Immediates to be used with logical XOR. This is almost, but not quite,
only an optimization. XOR with immediate is only supported with the
extended-immediate facility. That said, there are a few patterns for
which it is better to load the value into a register first. */
static int tcg_match_xori(TCGType type, tcg_target_long val)
{
if ((facilities & FACILITY_EXT_IMM) == 0) {
return 0;
}
if (type == TCG_TYPE_I32) {
/* All 32-bit XORs can be performed with 1 48-bit insn. */
return 1;
}
/* Look for negative values. These are best to load with LGHI. */
if (val < 0 && val == (int32_t)val) {
return 0;
}
return 1;
}
/* Test if a constant matches the constraint. */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
@ -505,10 +451,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
return val == (int32_t)val;
} else if (ct & TCG_CT_CONST_S33) {
return val >= -0xffffffffll && val <= 0xffffffffll;
} else if (ct & TCG_CT_CONST_ORI) {
return tcg_match_ori(type, val);
} else if (ct & TCG_CT_CONST_XORI) {
return tcg_match_xori(type, val);
} else if (ct & TCG_CT_CONST_NN16) {
return !(val < 0 && val == (int16_t)val);
} else if (ct & TCG_CT_CONST_NN32) {
return !(val < 0 && val == (int32_t)val);
} else if (ct & TCG_CT_CONST_U31) {
return val >= 0 && val <= 0x7fffffff;
} else if (ct & TCG_CT_CONST_ZERO) {
@ -2366,11 +2312,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static const TCGTargetOpDef r_rC = { 0, { "r", "rC" } };
static const TCGTargetOpDef r_rZ = { 0, { "r", "rZ" } };
static const TCGTargetOpDef r_r_ri = { 0, { "r", "r", "ri" } };
static const TCGTargetOpDef r_0_r = { 0, { "r", "0", "r" } };
static const TCGTargetOpDef r_0_ri = { 0, { "r", "0", "ri" } };
static const TCGTargetOpDef r_0_rI = { 0, { "r", "0", "rI" } };
static const TCGTargetOpDef r_0_rJ = { 0, { "r", "0", "rJ" } };
static const TCGTargetOpDef r_0_rO = { 0, { "r", "0", "rO" } };
static const TCGTargetOpDef r_0_rX = { 0, { "r", "0", "rX" } };
static const TCGTargetOpDef r_0_rN = { 0, { "r", "0", "rN" } };
static const TCGTargetOpDef r_0_rM = { 0, { "r", "0", "rM" } };
static const TCGTargetOpDef a2_r = { 0, { "r", "r", "0", "1", "r", "r" } };
static const TCGTargetOpDef a2_ri = { 0, { "r", "r", "0", "1", "ri", "r" } };
static const TCGTargetOpDef a2_rA = { 0, { "r", "r", "0", "1", "rA", "r" } };
@ -2416,11 +2363,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
case INDEX_op_or_i32:
/* The use of [iNM] constraints are optimization only, since a full
64-bit immediate OR can always be performed with 4 sequential
OI[LH][LH] instructions. By rejecting certain negative ranges,
the immediate load plus the reg-reg OR is smaller. */
return (s390_facilities & FACILITY_EXT_IMM
? &r_0_ri
: &r_0_rN);
case INDEX_op_or_i64:
return &r_0_rO;
return (s390_facilities & FACILITY_EXT_IMM
? &r_0_rM
: &r_0_rN);
case INDEX_op_xor_i32:
/* Without EXT_IMM, no immediates are supported. Otherwise,
rejecting certain negative ranges leads to smaller code. */
return (s390_facilities & FACILITY_EXT_IMM
? &r_0_ri
: &r_0_r);
case INDEX_op_xor_i64:
return &r_0_rX;
return (s390_facilities & FACILITY_EXT_IMM
? &r_0_rM
: &r_0_r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
return &r_0_ri;