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https://github.com/yuzu-emu/unicorn.git
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target/i386: move cpu_ptr0 to DisasContext
Backports commit 2ee2646491a293a92d1c85e90e12419a8c199ed0 from qemu
This commit is contained in:
Emilio G. Cota
Lioncash
parent
cc872aa711
commit
3e442d4480
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@ -123,6 +123,7 @@ typedef struct DisasContext {
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/* TCG local register indexes (only used inside old micro ops) */
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TCGv tmp0;
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TCGv tmp4;
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TCGv_ptr ptr0;
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sigjmp_buf jmpbuf;
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struct uc_struct *uc;
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@ -3495,7 +3496,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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TCGMemOp ot;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr cpu_env = tcg_ctx->cpu_env;
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TCGv_ptr cpu_ptr0 = tcg_ctx->cpu_ptr0;
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TCGv_ptr cpu_ptr1 = tcg_ctx->cpu_ptr1;
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TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
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TCGv_i32 cpu_tmp3_i32 = tcg_ctx->cpu_tmp3_i32;
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@ -3615,27 +3615,27 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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#endif
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{
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gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,fpregs[reg].mmx));
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tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, s->T0);
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gen_helper_movl_mm_T0_mmx(tcg_ctx, cpu_ptr0, cpu_tmp2_i32);
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gen_helper_movl_mm_T0_mmx(tcg_ctx, s->ptr0, cpu_tmp2_i32);
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}
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break;
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case 0x16e: /* movd xmm, ea */
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#ifdef TARGET_X86_64
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if (s->dflag == MO_64) {
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gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,xmm_regs[reg]));
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gen_helper_movq_mm_T0_xmm(tcg_ctx, cpu_ptr0, s->T0);
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gen_helper_movq_mm_T0_xmm(tcg_ctx, s->ptr0, s->T0);
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} else
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#endif
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{
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gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,xmm_regs[reg]));
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tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, s->T0);
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gen_helper_movl_mm_T0_xmm(tcg_ctx, cpu_ptr0, cpu_tmp2_i32);
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gen_helper_movl_mm_T0_xmm(tcg_ctx, s->ptr0, cpu_tmp2_i32);
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}
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break;
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case 0x6f: /* movq mm, ea */
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@ -3774,14 +3774,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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goto illegal_op;
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field_length = x86_ldub_code(env, s) & 0x3F;
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bit_index = x86_ldub_code(env, s) & 0x3F;
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,xmm_regs[reg]));
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if (b1 == 1)
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gen_helper_extrq_i(tcg_ctx, cpu_env, cpu_ptr0,
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gen_helper_extrq_i(tcg_ctx, cpu_env, s->ptr0,
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tcg_const_i32(tcg_ctx, bit_index),
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tcg_const_i32(tcg_ctx, field_length));
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else
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gen_helper_insertq_i(tcg_ctx, cpu_env, cpu_ptr0,
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gen_helper_insertq_i(tcg_ctx, cpu_env, s->ptr0,
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tcg_const_i32(tcg_ctx, bit_index),
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tcg_const_i32(tcg_ctx, field_length));
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}
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@ -3928,22 +3928,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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rm = (modrm & 7);
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op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
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}
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op2_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op2_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op1_offset);
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sse_fn_epp(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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sse_fn_epp(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0x050: /* movmskps */
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rm = (modrm & 7) | REX_B(s);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,xmm_regs[rm]));
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gen_helper_movmskps(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0);
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gen_helper_movmskps(tcg_ctx, cpu_tmp2_i32, cpu_env, s->ptr0);
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tcg_gen_extu_i32_tl(tcg_ctx, cpu_regs[reg], cpu_tmp2_i32);
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break;
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case 0x150: /* movmskpd */
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rm = (modrm & 7) | REX_B(s);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env,
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env,
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offsetof(CPUX86State,xmm_regs[rm]));
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gen_helper_movmskpd(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0);
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gen_helper_movmskpd(tcg_ctx, cpu_tmp2_i32, cpu_env, s->ptr0);
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tcg_gen_extu_i32_tl(tcg_ctx, cpu_regs[reg], cpu_tmp2_i32);
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break;
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case 0x02a: /* cvtpi2ps */
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@ -3958,15 +3958,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
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}
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op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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switch(b >> 8) {
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case 0x0:
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gen_helper_cvtpi2ps(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvtpi2ps(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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default:
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case 0x1:
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gen_helper_cvtpi2pd(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvtpi2pd(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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}
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break;
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@ -3975,15 +3975,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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ot = mo_64_32(s->dflag);
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gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
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op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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if (ot == MO_32) {
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SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
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tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, s->T0);
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sse_fn_epi(tcg_ctx, cpu_env, cpu_ptr0, cpu_tmp2_i32);
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sse_fn_epi(tcg_ctx, cpu_env, s->ptr0, cpu_tmp2_i32);
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} else {
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#ifdef TARGET_X86_64
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SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
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sse_fn_epl(tcg_ctx, cpu_env, cpu_ptr0, s->T0);
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sse_fn_epl(tcg_ctx, cpu_env, s->ptr0, s->T0);
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#else
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goto illegal_op;
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#endif
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@ -4003,20 +4003,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
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}
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op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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switch(b) {
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case 0x02c:
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gen_helper_cvttps2pi(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvttps2pi(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0x12c:
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gen_helper_cvttpd2pi(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvttpd2pi(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0x02d:
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gen_helper_cvtps2pi(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvtps2pi(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0x12d:
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gen_helper_cvtpd2pi(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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gen_helper_cvtpd2pi(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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}
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break;
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@ -4038,17 +4038,17 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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rm = (modrm & 7) | REX_B(s);
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op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
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}
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op2_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op2_offset);
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if (ot == MO_32) {
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SSEFunc_i_ep sse_fn_i_ep =
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sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
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sse_fn_i_ep(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0);
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sse_fn_i_ep(tcg_ctx, cpu_tmp2_i32, cpu_env, s->ptr0);
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tcg_gen_extu_i32_tl(tcg_ctx, s->T0, cpu_tmp2_i32);
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} else {
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#ifdef TARGET_X86_64
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SSEFunc_l_ep sse_fn_l_ep =
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sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
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sse_fn_l_ep(tcg_ctx, s->T0, cpu_env, cpu_ptr0);
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sse_fn_l_ep(tcg_ctx, s->T0, cpu_env, s->ptr0);
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#else
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goto illegal_op;
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#endif
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@ -4121,12 +4121,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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goto illegal_op;
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if (b1) {
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rm = (modrm & 7) | REX_B(s);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
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gen_helper_pmovmskb_xmm(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
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gen_helper_pmovmskb_xmm(tcg_ctx, cpu_tmp2_i32, cpu_env, s->ptr0);
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} else {
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rm = (modrm & 7);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
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gen_helper_pmovmskb_mmx(tcg_ctx, cpu_tmp2_i32, cpu_env, cpu_ptr0);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
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gen_helper_pmovmskb_mmx(tcg_ctx, cpu_tmp2_i32, cpu_env, s->ptr0);
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}
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reg = ((modrm >> 3) & 7) | rex_r;
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tcg_gen_extu_i32_tl(tcg_ctx, cpu_regs[reg], cpu_tmp2_i32);
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@ -4201,9 +4201,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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goto unknown_op;
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}
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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sse_fn_epp(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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sse_fn_epp(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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if (b == 0x17) {
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set_cc_op(s, CC_OP_EFLAGS);
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@ -4750,9 +4750,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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}
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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sse_fn_eppi(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(tcg_ctx, val));
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sse_fn_eppi(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1, tcg_const_i32(tcg_ctx, val));
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break;
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case 0x33a:
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@ -4870,18 +4870,18 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
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goto illegal_op;
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}
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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sse_fn_epp(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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sse_fn_epp(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0x70: /* pshufx insn */
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case 0xc6: /* pshufx insn */
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val = x86_ldub_code(env, s);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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/* XXX: introduce a new table? */
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sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
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sse_fn_ppi(tcg_ctx, cpu_ptr0, cpu_ptr1, tcg_const_i32(tcg_ctx, val));
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sse_fn_ppi(tcg_ctx, s->ptr0, cpu_ptr1, tcg_const_i32(tcg_ctx, val));
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break;
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case 0xc2:
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/* compare insns */
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@ -4890,9 +4890,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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goto unknown_op;
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sse_fn_epp = sse_op_table4[val][b1];
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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sse_fn_epp(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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sse_fn_epp(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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case 0xf7:
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/* maskmov : we must prepare A0 */
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@ -4902,16 +4902,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_extu(s, s->aflag, s->A0);
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gen_add_A0_ds_seg(s);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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/* XXX: introduce a new table? */
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sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
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sse_fn_eppt(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1, s->A0);
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sse_fn_eppt(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1, s->A0);
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break;
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default:
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(tcg_ctx, cpu_ptr1, cpu_env, op2_offset);
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sse_fn_epp(tcg_ctx, cpu_env, cpu_ptr0, cpu_ptr1);
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sse_fn_epp(tcg_ctx, cpu_env, s->ptr0, cpu_ptr1);
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break;
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}
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if (b == 0x2e || b == 0x2f) {
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@ -9137,7 +9137,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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tcg_ctx->cpu_tmp1_i64 = tcg_temp_new_i64(tcg_ctx);
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tcg_ctx->cpu_tmp2_i32 = tcg_temp_new_i32(tcg_ctx);
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tcg_ctx->cpu_tmp3_i32 = tcg_temp_new_i32(tcg_ctx);
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tcg_ctx->cpu_ptr0 = tcg_temp_new_ptr(tcg_ctx);
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dc->ptr0 = tcg_temp_new_ptr(tcg_ctx);
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tcg_ctx->cpu_ptr1 = tcg_temp_new_ptr(tcg_ctx);
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dc->cc_srcT = tcg_temp_local_new(tcg_ctx);
|
||||
|
|
|
|||
|
|
@ -827,7 +827,7 @@ struct TCGContext {
|
|||
TCGv cpu_cc_src2;
|
||||
|
||||
/* qemu/target-i386/translate.c: local register indexes (only used inside old micro ops) */
|
||||
TCGv_ptr cpu_ptr0, cpu_ptr1;
|
||||
TCGv_ptr cpu_ptr1;
|
||||
TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
|
||||
TCGv_i64 cpu_tmp1_i64;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue