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tcg/aarch64: Implement vector minmax arithmetic
Backports commit 93f332a50371936ea02392bdb748c8140ef3f06a from qemu
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@ -136,7 +136,7 @@ typedef enum {
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#define TCG_TARGET_HAS_cmp_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 0
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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@ -528,8 +528,12 @@ typedef enum {
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I3616_CMHI = 0x2e203400,
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I3616_CMHS = 0x2e203c00,
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I3616_CMEQ = 0x2e208c00,
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I3616_SMAX = 0x0e206400,
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I3616_SMIN = 0x0e206c00,
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I3616_SQADD = 0x0e200c00,
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I3616_SQSUB = 0x0e202c00,
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I3616_UMAX = 0x2e206400,
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I3616_UMIN = 0x2e206c00,
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I3616_UQADD = 0x2e200c00,
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I3616_UQSUB = 0x2e202c00,
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@ -2153,6 +2157,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_ussub_vec:
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tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
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break;
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case INDEX_op_smax_vec:
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tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
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break;
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case INDEX_op_smin_vec:
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tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);
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break;
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case INDEX_op_umax_vec:
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tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);
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break;
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case INDEX_op_umin_vec:
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tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);
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break;
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case INDEX_op_not_vec:
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tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
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break;
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@ -2227,6 +2243,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_sssub_vec:
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case INDEX_op_usadd_vec:
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case INDEX_op_ussub_vec:
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case INDEX_op_smax_vec:
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case INDEX_op_smin_vec:
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case INDEX_op_umax_vec:
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case INDEX_op_umin_vec:
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return 1;
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case INDEX_op_mul_vec:
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return vece < MO_64;
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@ -2410,6 +2430,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_sssub_vec:
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case INDEX_op_usadd_vec:
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case INDEX_op_ussub_vec:
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case INDEX_op_smax_vec:
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case INDEX_op_smin_vec:
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case INDEX_op_umax_vec:
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case INDEX_op_umin_vec:
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return &w_w_w;
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case INDEX_op_not_vec:
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case INDEX_op_neg_vec:
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