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target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac

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All remaining tests for VFP4 are for fused multiply-add insns.

Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.

Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.

Backports commit c52881bbc22b50db99a6c37171ad3eea7d959ae6 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 23:48:11 -04:00 committed by Lioncash
parent f6b5a9ef81
commit 3f0ae7ccee
3 changed files with 33 additions and 5 deletions
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12
qemu/target/arm/cpu.h
View file

@ -3387,6 +3387,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
/*
* Note that this ID register field covers both VFP and Neon FMAC,
* so should usually be tested in combination with some other
* check that confirms the presence of whichever of VFP or Neon is
* relevant, to avoid accidentally enabling a Neon feature on
* a VFP-no-Neon core or vice-versa.
*/
static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
{
return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
}
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;

24
qemu/target/arm/translate-vfp.inc.c
View file

@ -1828,11 +1828,19 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
/*
* Present in VFPv4 only.
* Note that we can't rely on the SIMDFMAC check alone, because
* in a Neon-no-VFP core that ID register field will be non-zero.
*/
if (!dc_isar_feature(aa32_simdfmac, s) ||
!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
/*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
(s->vec_len != 0 || s->vec_stride != 0)) {
if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
@ -1887,11 +1895,19 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
/*
* Present in VFPv4 only.
* Note that we can't rely on the SIMDFMAC check alone, because
* in a Neon-no-VFP core that ID register field will be non-zero.
*/
if (!dc_isar_feature(aa32_simdfmac, s) ||
!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
/*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
(s->vec_len != 0 || s->vec_stride != 0)) {
if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}

2
qemu/target/arm/translate.c
View file

@ -5283,7 +5283,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
break;
case NEON_3R_VFM_VQRDMLSH:
if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
if (!dc_isar_feature(aa32_simdfmac, s)) {
return 1;
}
break;