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target-arm: Add and use symbolic names for register banks

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Add BANK_<cpumode> #defines to index banked registers.

Backports commit 99a99c1fc8e9bfec1656ac5916c53977a93d3581 from qemu
This commit is contained in:
Soren Brinkmann 2018-02-17 18:13:51 -05:00 committed by Lioncash
parent 085a89bef5
commit 3f4efdd95e
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 33 additions and 23 deletions
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30
qemu/target-arm/helper.c
View file

@ -2789,7 +2789,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "ELR_EL1", 0,4,0, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[1]) },
{ "SPSR_EL1", 0,4,0, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[1]) },
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
@ -2908,15 +2908,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
{ "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[6]) },
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
{ "SPSR_IRQ", 0,4,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[4]) },
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
{ "SPSR_ABT", 0,4,3, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[2]) },
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
{ "SPSR_UND", 0,4,3, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[3]) },
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_UND]) },
{ "SPSR_FIQ", 0,4,3, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[5]) },
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
{ "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[2]), {0, 0},
NULL, NULL, vbar_write, },
@ -3075,7 +3075,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "FAR_EL3", 0,6,0, 3,6,0, ARM_CP_STATE_AA64,
0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[3]) },
{ "SPSR_EL3", 0,4,0, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[7]) },
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_MON]) },
{ "VBAR_EL3", 0,12,0, 3,6,0, ARM_CP_STATE_AA64,
0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[3]), {0, 0},
NULL, NULL, vbar_write, },
@ -4528,21 +4528,21 @@ int bank_number(int mode)
default:
case ARM_CPU_MODE_USR:
case ARM_CPU_MODE_SYS:
return 0;
return BANK_USRSYS;
case ARM_CPU_MODE_SVC:
return 1;
return BANK_SVC;
case ARM_CPU_MODE_ABT:
return 2;
return BANK_ABT;
case ARM_CPU_MODE_UND:
return 3;
return BANK_UND;
case ARM_CPU_MODE_IRQ:
return 4;
return BANK_IRQ;
case ARM_CPU_MODE_FIQ:
return 5;
return BANK_FIQ;
case ARM_CPU_MODE_HYP:
return 6;
return BANK_HYP;
case ARM_CPU_MODE_MON:
return 7;
return BANK_MON;
}
g_assert_not_reached();
}

18
qemu/target-arm/internals.h
View file

@ -25,6 +25,16 @@
#ifndef TARGET_ARM_INTERNALS_H
#define TARGET_ARM_INTERNALS_H
/* register banks for CPU modes */
#define BANK_USRSYS 0
#define BANK_SVC 1
#define BANK_ABT 2
#define BANK_UND 3
#define BANK_IRQ 4
#define BANK_FIQ 5
#define BANK_HYP 6
#define BANK_MON 7
static inline bool excp_is_internal(int excp)
{
/* Return true if this exception number represents a QEMU-internal
@ -92,10 +102,10 @@ static inline void arm_log_exception(int idx)
static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
{
static const unsigned int map[4] = {
0,
1, /* EL1. */
6, /* EL2. */
7, /* EL3. */
BANK_USRSYS,
BANK_SVC, /* EL1. */
BANK_HYP, /* EL2. */
BANK_MON, /* EL3. */
};
assert(el >= 1 && el <= 3);
return map[el];

8
qemu/target-arm/op_helper.c
View file

@ -392,9 +392,9 @@ uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
uint32_t val;
if (regno == 13) {
val = env->banked_r13[0];
val = env->banked_r13[BANK_USRSYS];
} else if (regno == 14) {
val = env->banked_r14[0];
val = env->banked_r14[BANK_USRSYS];
} else if (regno >= 8
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
val = env->usr_regs[regno - 8];
@ -407,9 +407,9 @@ uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
{
if (regno == 13) {
env->banked_r13[0] = val;
env->banked_r13[BANK_USRSYS] = val;
} else if (regno == 14) {
env->banked_r14[0] = val;
env->banked_r14[BANK_USRSYS] = val;
} else if (regno >= 8
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
env->usr_regs[regno - 8] = val;