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target/mips: Clean up handling of CP0 register 12

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Clean up handling of CP0 register 12.

Backports commit 2b0848674b4143bf5b2b6f7de6b8587dd52c31dd from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 23:06:36 -05:00 committed by Lioncash
parent 5812937c52
commit 3f76658fd8
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 19 additions and 16 deletions
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3
qemu/target/mips/cpu.h
View file

@ -349,6 +349,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
#define CP0_REG12__SRSMAP 3
#define CP0_REG12__VIEW_IPL 4
#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */

32
qemu/target/mips/translate.c
View file

@ -7256,21 +7256,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
case 0:
case CP0_REG12__STATUS:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
case 1:
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case 2:
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case 3:
case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@ -7973,7 +7973,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
case 0:
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(tcg_ctx, tcg_ctx->cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@ -7981,21 +7981,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
case 1:
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case 2:
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case 3:
case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@ -8728,21 +8728,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
case 0:
case CP0_REG12__STATUS:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
case 1:
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case 2:
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case 3:
case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@ -9429,7 +9429,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
case 0:
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(tcg_ctx, tcg_ctx->cpu_env, arg);
/* BS_STOP isn't good enough here, hflags may have changed. */
@ -9437,21 +9437,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
case 1:
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case 2:
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(tcg_ctx, tcg_ctx->cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case 3:
case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */