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exec: introduce cpu_reload_memory_map

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This for now is a simple TLB flush. This can change later for two
reasons:

1) an AddressSpaceDispatch will be cached in the CPUState object

2) it will not be possible to do tlb_flush once the TCG-generated code
runs outside the BQL.

Backports commit 76e5c76f2e2e0d20bab2cd5c7a87452f711654fb from qemu
This commit is contained in:
Paolo Bonzini 2018-02-12 15:09:20 -05:00 committed by Lioncash
parent 8287ec801e
commit 3fbda890df
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
17 changed files with 22 additions and 1 deletions
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1
qemu/aarch64.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_aarch64
#define memory_register_types memory_register_types_aarch64
#define cpu_exec_init_all cpu_exec_init_all_aarch64
#define cpu_reload_memory_map cpu_reload_memory_map_aarch64
#define vm_start vm_start_aarch64
#define resume_all_vcpus resume_all_vcpus_aarch64
#define a15_l2ctlr_read a15_l2ctlr_read_aarch64

1
qemu/aarch64eb.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_aarch64eb
#define memory_register_types memory_register_types_aarch64eb
#define cpu_exec_init_all cpu_exec_init_all_aarch64eb
#define cpu_reload_memory_map cpu_reload_memory_map_aarch64eb
#define vm_start vm_start_aarch64eb
#define resume_all_vcpus resume_all_vcpus_aarch64eb
#define a15_l2ctlr_read a15_l2ctlr_read_aarch64eb

1
qemu/arm.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_arm
#define memory_register_types memory_register_types_arm
#define cpu_exec_init_all cpu_exec_init_all_arm
#define cpu_reload_memory_map cpu_reload_memory_map_arm
#define vm_start vm_start_arm
#define resume_all_vcpus resume_all_vcpus_arm
#define a15_l2ctlr_read a15_l2ctlr_read_arm

1
qemu/armeb.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_armeb
#define memory_register_types memory_register_types_armeb
#define cpu_exec_init_all cpu_exec_init_all_armeb
#define cpu_reload_memory_map cpu_reload_memory_map_armeb
#define vm_start vm_start_armeb
#define resume_all_vcpus resume_all_vcpus_armeb
#define a15_l2ctlr_read a15_l2ctlr_read_armeb

6
qemu/cpu-exec.c
View file

@ -286,6 +286,12 @@ int cpu_exec(struct uc_struct *uc, CPUArchState *env) // qq
return ret;
}
void cpu_reload_memory_map(CPUState *cpu)
{
/* The TLB is protected by the iothread lock. */
tlb_flush(cpu, 1);
}
/* Execute a TB, and fix up the CPU state afterwards if necessary */
static tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
{

2
qemu/exec.c
View file

@ -1484,7 +1484,7 @@ static void tcg_commit(MemoryListener *listener)
/* since each CPU stores ram addresses in its TLB cache, we must
reset the modified entries */
/* XXX: slow ! */
tlb_flush(uc->cpu, 1);
cpu_reload_memory_map(uc->cpu);
}
void address_space_init_dispatch(AddressSpace *as)

1
qemu/header_gen.py
View file

@ -30,6 +30,7 @@ symbols = (
'tcg_exec_init',
'memory_register_types',
'cpu_exec_init_all',
'cpu_reload_memory_map',
'vm_start',
'resume_all_vcpus',
'a15_l2ctlr_read',

1
qemu/include/exec/exec-all.h
View file

@ -92,6 +92,7 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
void tb_invalidate_phys_range(struct uc_struct *uc, tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
void cpu_reload_memory_map(CPUState *cpu);
void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUState *cpu, target_ulong addr);

1
qemu/m68k.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_m68k
#define memory_register_types memory_register_types_m68k
#define cpu_exec_init_all cpu_exec_init_all_m68k
#define cpu_reload_memory_map cpu_reload_memory_map_m68k
#define vm_start vm_start_m68k
#define resume_all_vcpus resume_all_vcpus_m68k
#define a15_l2ctlr_read a15_l2ctlr_read_m68k

1
qemu/mips.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_mips
#define memory_register_types memory_register_types_mips
#define cpu_exec_init_all cpu_exec_init_all_mips
#define cpu_reload_memory_map cpu_reload_memory_map_mips
#define vm_start vm_start_mips
#define resume_all_vcpus resume_all_vcpus_mips
#define a15_l2ctlr_read a15_l2ctlr_read_mips

1
qemu/mips64.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_mips64
#define memory_register_types memory_register_types_mips64
#define cpu_exec_init_all cpu_exec_init_all_mips64
#define cpu_reload_memory_map cpu_reload_memory_map_mips64
#define vm_start vm_start_mips64
#define resume_all_vcpus resume_all_vcpus_mips64
#define a15_l2ctlr_read a15_l2ctlr_read_mips64

1
qemu/mips64el.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_mips64el
#define memory_register_types memory_register_types_mips64el
#define cpu_exec_init_all cpu_exec_init_all_mips64el
#define cpu_reload_memory_map cpu_reload_memory_map_mips64el
#define vm_start vm_start_mips64el
#define resume_all_vcpus resume_all_vcpus_mips64el
#define a15_l2ctlr_read a15_l2ctlr_read_mips64el

1
qemu/mipsel.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_mipsel
#define memory_register_types memory_register_types_mipsel
#define cpu_exec_init_all cpu_exec_init_all_mipsel
#define cpu_reload_memory_map cpu_reload_memory_map_mipsel
#define vm_start vm_start_mipsel
#define resume_all_vcpus resume_all_vcpus_mipsel
#define a15_l2ctlr_read a15_l2ctlr_read_mipsel

1
qemu/powerpc.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_powerpc
#define memory_register_types memory_register_types_powerpc
#define cpu_exec_init_all cpu_exec_init_all_powerpc
#define cpu_reload_memory_map cpu_reload_memory_map_powerpc
#define vm_start vm_start_powerpc
#define resume_all_vcpus resume_all_vcpus_powerpc
#define a15_l2ctlr_read a15_l2ctlr_read_powerpc

1
qemu/sparc.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_sparc
#define memory_register_types memory_register_types_sparc
#define cpu_exec_init_all cpu_exec_init_all_sparc
#define cpu_reload_memory_map cpu_reload_memory_map_sparc
#define vm_start vm_start_sparc
#define resume_all_vcpus resume_all_vcpus_sparc
#define a15_l2ctlr_read a15_l2ctlr_read_sparc

1
qemu/sparc64.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_sparc64
#define memory_register_types memory_register_types_sparc64
#define cpu_exec_init_all cpu_exec_init_all_sparc64
#define cpu_reload_memory_map cpu_reload_memory_map_sparc64
#define vm_start vm_start_sparc64
#define resume_all_vcpus resume_all_vcpus_sparc64
#define a15_l2ctlr_read a15_l2ctlr_read_sparc64

1
qemu/x86_64.h
View file

@ -24,6 +24,7 @@
#define tcg_exec_init tcg_exec_init_x86_64
#define memory_register_types memory_register_types_x86_64
#define cpu_exec_init_all cpu_exec_init_all_x86_64
#define cpu_reload_memory_map cpu_reload_memory_map_x86_64
#define vm_start vm_start_x86_64
#define resume_all_vcpus resume_all_vcpus_x86_64
#define a15_l2ctlr_read a15_l2ctlr_read_x86_64