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target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Backports commit 476a4692f06e381117fb7ad0d04d37c9c2612198 from qemu
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@ -2924,8 +2924,7 @@ FIELD(TBFLAG_A32, HANDLER, 21, 1)
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FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
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FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
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/* Bit usage when in AArch64 state */
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/* Bit usage when in AArch64 state */
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FIELD(TBFLAG_A64, TBI0, 0, 1)
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FIELD(TBFLAG_A64, TBII, 0, 2)
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FIELD(TBFLAG_A64, TBI1, 1, 1)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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@ -12249,10 +12249,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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*pc = env->pc;
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*pc = env->pc;
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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/* Get control bits for tagged addresses */
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/* Get control bits for tagged addresses */
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flags = FIELD_DP32(flags, TBFLAG_A64, TBI0,
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flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
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(arm_regime_tbi1(env, mmu_idx) << 1) |
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arm_regime_tbi0(env, mmu_idx));
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arm_regime_tbi0(env, mmu_idx));
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flags = FIELD_DP32(flags, TBFLAG_A64, TBI1,
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arm_regime_tbi1(env, mmu_idx));
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if (cpu_isar_feature(aa64_sve, cpu)) {
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if (cpu_isar_feature(aa64_sve, cpu)) {
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int sve_el = sve_exception_el(env, current_el);
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int sve_el = sve_exception_el(env, current_el);
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@ -294,13 +294,15 @@ void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
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static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
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static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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/* Note that TBII is TBI1:TBI0. */
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int tbi = s->tbii;
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if (s->current_el <= 1) {
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if (s->current_el <= 1) {
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/* Test if NEITHER or BOTH TBI values are set. If so, no need to
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/* Test if NEITHER or BOTH TBI values are set. If so, no need to
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* examine bit 55 of address, can just generate code.
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* examine bit 55 of address, can just generate code.
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* If mixed, then test via generated code
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* If mixed, then test via generated code
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*/
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*/
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if (s->tbi0 && s->tbi1) {
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if (tbi == 3) {
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TCGv_i64 tmp_reg = tcg_temp_new_i64(tcg_ctx);
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TCGv_i64 tmp_reg = tcg_temp_new_i64(tcg_ctx);
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/* Both bits set, sign extension from bit 55 into [63:56] will
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/* Both bits set, sign extension from bit 55 into [63:56] will
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* cover both cases
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* cover both cases
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@ -308,7 +310,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
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tcg_gen_shli_i64(tcg_ctx, tmp_reg, src, 8);
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tcg_gen_shli_i64(tcg_ctx, tmp_reg, src, 8);
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tcg_gen_sari_i64(tcg_ctx, tcg_ctx->cpu_pc, tmp_reg, 8);
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tcg_gen_sari_i64(tcg_ctx, tcg_ctx->cpu_pc, tmp_reg, 8);
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tcg_temp_free_i64(tcg_ctx, tmp_reg);
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tcg_temp_free_i64(tcg_ctx, tmp_reg);
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} else if (!s->tbi0 && !s->tbi1) {
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} else if (tbi == 0) {
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/* Neither bit set, just load it as-is */
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/* Neither bit set, just load it as-is */
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_pc, src);
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_pc, src);
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} else {
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} else {
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@ -318,7 +320,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
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tcg_gen_andi_i64(tcg_ctx, tcg_bit55, src, (1ull << 55));
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tcg_gen_andi_i64(tcg_ctx, tcg_bit55, src, (1ull << 55));
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if (s->tbi0) {
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if (tbi == 1) {
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/* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
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/* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
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tcg_gen_andi_i64(tcg_ctx, tcg_tmpval, src,
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tcg_gen_andi_i64(tcg_ctx, tcg_tmpval, src,
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0x00FFFFFFFFFFFFFFull);
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0x00FFFFFFFFFFFFFFull);
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@ -336,7 +338,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
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tcg_temp_free_i64(tcg_ctx, tcg_tmpval);
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tcg_temp_free_i64(tcg_ctx, tcg_tmpval);
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}
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}
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} else { /* EL > 1 */
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} else { /* EL > 1 */
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if (s->tbi0) {
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if (tbi != 0) {
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/* Force tag byte to all zero */
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/* Force tag byte to all zero */
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tcg_gen_andi_i64(tcg_ctx, tcg_ctx->cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
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tcg_gen_andi_i64(tcg_ctx, tcg_ctx->cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
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} else {
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} else {
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@ -14004,8 +14006,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->condexec_cond = 0;
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dc->condexec_cond = 0;
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core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
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core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
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dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
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dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
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dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0);
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dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
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dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1);
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dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
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dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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dc->user = (dc->current_el == 0);
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dc->user = (dc->current_el == 0);
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@ -25,8 +25,7 @@ typedef struct DisasContext {
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int user;
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int user;
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#endif
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#endif
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */
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uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */
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bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */
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bool ns; /* Use non-secure CPREG bank on access */
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bool ns; /* Use non-secure CPREG bank on access */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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