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target/arm: Convert Neon 64-bit element 3-reg-same insns

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Convert the 64-bit element insns in the 3-reg-same group
to decodetree. This covers VQSHL, VRSHL and VQRSHL where
size==0b11.

Backports commit 35d4352fa9e94b35bf17f58181cb16c184b98d56 from qemu
This commit is contained in:
Peter Maydell 2020-05-15 22:38:53 -04:00 committed by Lioncash
parent e2b703a82c
commit 4098e0b80a
3 changed files with 39 additions and 36 deletions
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13
qemu/target/arm/neon-dp.decode
View file

@ -81,6 +81,19 @@ VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
# Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
# The _rev suffix indicates that Vn and Vm are reversed (as explained
# by the comment for the @3same_rev format).
@3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \
&3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same

24
qemu/target/arm/translate-neon.inc.c
View file

@ -842,3 +842,27 @@ static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
return true;
}
#define DO_3SAME_64(INSN, FUNC) \
static void gen_##INSN##_3s(TCGContext *s, unsigned vece, uint32_t rd_ofs, \
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
static const GVecGen3 op = { .fni8 = FUNC }; \
tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \
} \
DO_3SAME(INSN, gen_##INSN##_3s)
#define DO_3SAME_64_ENV(INSN, FUNC) \
static void gen_##INSN##_elt(TCGContext *s, TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
{ \
FUNC(s, d, s->cpu_env, n, m); \
} \
DO_3SAME_64(INSN, gen_##INSN##_elt)
DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64)
DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64)
DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64)
DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64)
DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64)
DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)

38
qemu/target/arm/translate.c
View file

@ -5586,42 +5586,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
if (size == 3) {
/* 64-bit element instructions. */
for (pass = 0; pass < (q ? 2 : 1); pass++) {
neon_load_reg64(s, s->V0, rn + pass);
neon_load_reg64(s, s->V1, rm + pass);
switch (op) {
case NEON_3R_VQSHL:
if (u) {
gen_helper_neon_qshl_u64(tcg_ctx, s->V0, tcg_ctx->cpu_env,
s->V1, s->V0);
} else {
gen_helper_neon_qshl_s64(tcg_ctx, s->V0, tcg_ctx->cpu_env,
s->V1, s->V0);
}
break;
case NEON_3R_VRSHL:
if (u) {
gen_helper_neon_rshl_u64(tcg_ctx, s->V0, s->V1, s->V0);
} else {
gen_helper_neon_rshl_s64(tcg_ctx, s->V0, s->V1, s->V0);
}
break;
case NEON_3R_VQRSHL:
if (u) {
gen_helper_neon_qrshl_u64(tcg_ctx, s->V0, tcg_ctx->cpu_env,
s->V1, s->V0);
} else {
gen_helper_neon_qrshl_s64(tcg_ctx, s->V0, tcg_ctx->cpu_env,
s->V1, s->V0);
}
break;
default:
abort();
}
neon_store_reg64(s, s->V0, rd + pass);
}
return 0;
/* 64-bit element instructions: handled by decodetree */
return 1;
}
pairwise = 0;
switch (op) {