target-mips: Provide function to test if a CPU supports an ISA

Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.

An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.

Backports commit bed9e5ceb158c886d548fe59675a6eba18baeaeb from qemu

qemu/header_gen.py

@@ -3505,6 +3505,7 @@ mips_symbols = (
     'cpu_rddsp',
     'cpu_set_exception_base',
     'cpu_state_reset',
+    'cpu_supports_isa',
     'cpu_wrdsp',
     'do_raise_exception_err',
     'exception_resume_pc',

qemu/mips.h

@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips
 #define cpu_set_exception_base cpu_set_exception_base_mips
 #define cpu_state_reset cpu_state_reset_mips
+#define cpu_supports_isa cpu_supports_isa_mips
 #define cpu_wrdsp cpu_wrdsp_mips
 #define do_raise_exception_err do_raise_exception_err_mips
 #define exception_resume_pc exception_resume_pc_mips

qemu/mips64.h

@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips64
 #define cpu_set_exception_base cpu_set_exception_base_mips64
 #define cpu_state_reset cpu_state_reset_mips64
+#define cpu_supports_isa cpu_supports_isa_mips64
 #define cpu_wrdsp cpu_wrdsp_mips64
 #define do_raise_exception_err do_raise_exception_err_mips64
 #define exception_resume_pc exception_resume_pc_mips64

qemu/mips64el.h

@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mips64el
 #define cpu_set_exception_base cpu_set_exception_base_mips64el
 #define cpu_state_reset cpu_state_reset_mips64el
+#define cpu_supports_isa cpu_supports_isa_mips64el
 #define cpu_wrdsp cpu_wrdsp_mips64el
 #define do_raise_exception_err do_raise_exception_err_mips64el
 #define exception_resume_pc exception_resume_pc_mips64el

qemu/mipsel.h

@@ -3441,6 +3441,7 @@
 #define cpu_rddsp cpu_rddsp_mipsel
 #define cpu_set_exception_base cpu_set_exception_base_mipsel
 #define cpu_state_reset cpu_state_reset_mipsel
+#define cpu_supports_isa cpu_supports_isa_mipsel
 #define cpu_wrdsp cpu_wrdsp_mipsel
 #define do_raise_exception_err do_raise_exception_err_mipsel
 #define exception_resume_pc exception_resume_pc_mipsel

qemu/target/mips/cpu.h

@@ -807,6 +807,7 @@ int cpu_mips_exec(struct uc_struct *uc, CPUState *cpu);
 void mips_tcg_init(struct uc_struct *uc);
 MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model);
 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
 void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address);
 
 /* TODO QOM'ify CPU reset and remove */

qemu/target/mips/translate.c

@@ -20367,6 +20367,16 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model)
     return cpu;
 }
 
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
+{
+    const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
+    if (!def) {
+        return false;
+    }
+
+    return (def->insn_flags & isa) != 0;
+}
+
 void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address)
 {
     MIPSCPU *vp = MIPS_CPU(uc, qemu_get_cpu(uc, vp_index));