mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-02-02 08:51:06 +00:00
target/mips: Prepare loads/stores for EVA
EVA load and store instructions access the user mode address map, so they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility functions to allow mem_idx to be more easily overridden from the decoding logic. Specifically we add a mem_idx argument to the op_ld/st_* helpers used for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and gen_st_cond(). Backports commit dd4096cd2ccc19384770f336c930259da7a54980 from qemu
This commit is contained in:
James Hogan
Lioncash
parent
152323fe35
commit
42a5534ade
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@ -2027,8 +2027,10 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
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/* load/store instructions. */
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#ifdef CONFIG_USER_ONLY
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#define OP_LD_ATOMIC(insn,fname) \
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static inline void op_ld_##insn(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, DisasContext *ctx) \
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static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
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DisasContext *ctx) \
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{ \
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx; \
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TCGv t0 = tcg_temp_new(tcg_ctx); \
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tcg_gen_mov_tl(tcg_ctx, t0, arg1); \
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tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
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@ -2038,9 +2040,11 @@ static inline void op_ld_##insn(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, DisasC
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}
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#else
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#define OP_LD_ATOMIC(insn,fname) \
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static inline void op_ld_##insn(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, DisasContext *ctx) \
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static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
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DisasContext *ctx) \
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{ \
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gen_helper_1e1i(tcg_ctx, insn, ret, arg1, ctx->mem_idx); \
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx; \
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gen_helper_1e1i(tcg_ctx, insn, ret, arg1, mem_idx); \
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}
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#endif
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OP_LD_ATOMIC(ll,ld32s);
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@ -2051,9 +2055,10 @@ OP_LD_ATOMIC(lld,ld64);
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#ifdef CONFIG_USER_ONLY
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#define OP_ST_ATOMIC(insn,fname,ldname,almask) \
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static inline void op_st_##insn(DisasContext *s, TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
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static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx, \
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DisasContext *ctx) \
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{ \
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TCGContext *tcg_ctx = s->uc->tcg_ctx; \
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx; \
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TCGv t0 = tcg_temp_new(tcg_ctx); \
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TCGLabel *l1 = gen_new_label(tcg_ctx); \
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TCGLabel *l2 = gen_new_label(tcg_ctx); \
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@ -2076,8 +2081,10 @@ static inline void op_st_##insn(DisasContext *s, TCGv arg1, TCGv arg2, int rt, D
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}
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#else
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#define OP_ST_ATOMIC(insn,fname,ldname,almask) \
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static inline void op_st_##insn(TCGContext *tcg_ctx, TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
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static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx, \
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DisasContext *ctx) \
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{ \
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx; \
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TCGv t0 = tcg_temp_new(tcg_ctx); \
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gen_helper_1e2i(tcg_ctx, insn, t0, arg1, arg2, ctx->mem_idx); \
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gen_store_gpr(tcg_ctx, t0, rt); \
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@ -2125,6 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1, t2;
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int mem_idx = ctx->mem_idx;
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if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
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/* Loongson CPU uses a load to zero register for prefetch.
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@ -2139,32 +2147,32 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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switch (opc) {
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#if defined(TARGET_MIPS64)
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case OPC_LWU:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEUL |
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEUL |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LD:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEQ |
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LLD:
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case R6_OPC_LLD:
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op_ld_lld(tcg_ctx, t0, t0, ctx);
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op_ld_lld(t0, t0, mem_idx, ctx);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LDL:
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t1 = tcg_temp_new(tcg_ctx);
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
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tcg_gen_andi_tl(tcg_ctx, t1, t0, 7);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 7);
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#endif
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tcg_gen_shli_tl(tcg_ctx, t1, t1, 3);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, ~7);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEQ);
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tcg_gen_shl_tl(tcg_ctx, t0, t0, t1);
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t2 = tcg_const_tl(tcg_ctx, -1);
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tcg_gen_shl_tl(tcg_ctx, t2, t2, t1);
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@ -2179,14 +2187,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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t1 = tcg_temp_new(tcg_ctx);
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
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tcg_gen_andi_tl(tcg_ctx, t1, t0, 7);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 7);
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#endif
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tcg_gen_shli_tl(tcg_ctx, t1, t1, 3);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, ~7);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEQ);
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tcg_gen_shr_tl(tcg_ctx, t0, t0, t1);
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 63);
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t2 = tcg_const_tl(tcg_ctx, 0xfffffffffffffffeull);
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@ -2202,7 +2210,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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t1 = tcg_const_tl(tcg_ctx, pc_relative_pc(ctx));
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gen_op_addr_add(ctx, t0, t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEQ);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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#endif
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@ -2210,44 +2218,44 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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t1 = tcg_const_tl(tcg_ctx, pc_relative_pc(ctx));
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gen_op_addr_add(ctx, t0, t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TESL);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TESL);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LW:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TESL |
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TESL |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LH:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TESW |
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TESW |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LHU:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEUW |
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEUW |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LB:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_SB);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_SB);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LBU:
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_UB);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_UB);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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case OPC_LWL:
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t1 = tcg_temp_new(tcg_ctx);
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
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tcg_gen_andi_tl(tcg_ctx, t1, t0, 3);
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#ifndef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 3);
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#endif
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tcg_gen_shli_tl(tcg_ctx, t1, t1, 3);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, ~3);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEUL);
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tcg_gen_shl_tl(tcg_ctx, t0, t0, t1);
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t2 = tcg_const_tl(tcg_ctx, -1);
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tcg_gen_shl_tl(tcg_ctx, t2, t2, t1);
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@ -2263,14 +2271,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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t1 = tcg_temp_new(tcg_ctx);
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/* Do a byte access to possibly trigger a page
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fault with the unaligned address. */
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, mem_idx, MO_UB);
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tcg_gen_andi_tl(tcg_ctx, t1, t0, 3);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 3);
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#endif
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tcg_gen_shli_tl(tcg_ctx, t1, t1, 3);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, ~3);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_ld_tl(ctx->uc, t0, t0, mem_idx, MO_TEUL);
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tcg_gen_shr_tl(tcg_ctx, t0, t0, t1);
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tcg_gen_xori_tl(tcg_ctx, t1, t1, 31);
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t2 = tcg_const_tl(tcg_ctx, 0xfffffffeull);
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@ -2285,7 +2293,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_LL:
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case R6_OPC_LL:
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op_ld_ll(tcg_ctx, t0, t0, ctx);
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op_ld_ll(t0, t0, mem_idx, ctx);
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gen_store_gpr(tcg_ctx, t0, rt);
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break;
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}
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@ -2299,38 +2307,39 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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int mem_idx = ctx->mem_idx;
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gen_base_offset_addr(ctx, t0, base, offset);
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gen_load_gpr(ctx, t1, rt);
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switch (opc) {
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#if defined(TARGET_MIPS64)
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case OPC_SD:
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_TEQ |
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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break;
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case OPC_SDL:
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gen_helper_0e2i(tcg_ctx, sdl, t1, t0, ctx->mem_idx);
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gen_helper_0e2i(tcg_ctx, sdl, t1, t0, mem_idx);
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break;
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case OPC_SDR:
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gen_helper_0e2i(tcg_ctx, sdr, t1, t0, ctx->mem_idx);
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gen_helper_0e2i(tcg_ctx, sdr, t1, t0, mem_idx);
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break;
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#endif
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case OPC_SW:
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_TEUL |
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, mem_idx, MO_TEUL |
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ctx->default_tcg_memop_mask);
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break;
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case OPC_SH:
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_TEUW |
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, mem_idx, MO_TEUW |
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ctx->default_tcg_memop_mask);
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break;
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case OPC_SB:
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_8);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, mem_idx, MO_8);
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break;
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case OPC_SWL:
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gen_helper_0e2i(tcg_ctx, swl, t1, t0, ctx->mem_idx);
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gen_helper_0e2i(tcg_ctx, swl, t1, t0, mem_idx);
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break;
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case OPC_SWR:
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gen_helper_0e2i(tcg_ctx, swr, t1, t0, ctx->mem_idx);
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gen_helper_0e2i(tcg_ctx, swr, t1, t0, mem_idx);
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break;
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}
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tcg_temp_free(tcg_ctx, t0);
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@ -2344,6 +2353,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1;
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int mem_idx = ctx->mem_idx;
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#ifdef CONFIG_USER_ONLY
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t0 = tcg_temp_local_new(tcg_ctx);
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@ -2358,12 +2368,12 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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#if defined(TARGET_MIPS64)
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case OPC_SCD:
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case R6_OPC_SCD:
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op_st_scd(tcg_ctx, t1, t0, rt, ctx);
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op_st_scd(t1, t0, rt, mem_idx, ctx);
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break;
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#endif
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case OPC_SC:
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case R6_OPC_SC:
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op_st_sc(tcg_ctx, t1, t0, rt, ctx);
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op_st_sc(t1, t0, rt, mem_idx, ctx);
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break;
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}
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tcg_temp_free(tcg_ctx, t1);
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