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target/arm: Implement VSCCLRM insn
Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. This requires support in write_neon_element32() for the MO_32 element size, so add it. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up in translate.c so it is before the #include of translate-vfp.c.inc. Backports 83ff3d6add965c9752324de11eac5687121ea826
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@ -3405,6 +3405,15 @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
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return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
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}
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static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
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{
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/*
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* Return true if M-profile state handling insns
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* (VSCCLRM, CLRM, FPCTX access insns) are implemented
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*/
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return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
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}
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static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
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{
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/* Sadly this is encoded differently for A-profile and M-profile */
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@ -29,13 +29,17 @@
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# If the coprocessor is not present or disabled then we will generate
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# the NOCP exception; otherwise we let the insn through to the main decode.
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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&nocp cp
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{
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# Special cases which do not take an early NOCP: VLLDM and VLSTM
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VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
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# TODO: VSCCLRM (new in v8.1M) is similar:
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#VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
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# VSCCLRM (new in v8.1M) is similar:
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VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3
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VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2
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NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
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NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
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@ -3468,6 +3468,91 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
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return true;
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}
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static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int btmreg, topreg;
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TCGv_i64 zero;
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TCGv_i32 aspen, sfpa;
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if (!dc_isar_feature(aa32_m_sec_state, s)) {
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/* Before v8.1M, fall through in decode to NOCP check */
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return false;
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}
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/* Explicitly UNDEF because this takes precedence over NOCP */
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if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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if (!dc_isar_feature(aa32_vfp_simd, s)) {
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/* NOP if we have neither FP nor MVE */
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return true;
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}
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/*
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* If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
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* active floating point context so we must NOP (without doing
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* any lazy state preservation or the NOCP check).
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*/
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aspen = load_cpu_field(s, v7m.fpccr[M_REG_S]);
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sfpa = load_cpu_field(s, v7m.control[M_REG_S]);
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tcg_gen_andi_i32(tcg_ctx, aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_xori_i32(tcg_ctx, aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_andi_i32(tcg_ctx, sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
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tcg_gen_or_i32(tcg_ctx, sfpa, sfpa, aspen);
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arm_gen_condlabel(s);
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, sfpa, 0, s->condlabel);
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if (s->fp_excp_el != 0) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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return true;
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}
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topreg = a->vd + a->imm - 1;
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btmreg = a->vd;
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/* Convert to Sreg numbers if the insn specified in Dregs */
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if (a->size == 3) {
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topreg = topreg * 2 + 1;
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btmreg *= 2;
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}
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if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
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/* UNPREDICTABLE: we choose to undef */
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unallocated_encoding(s);
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return true;
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}
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/* Silently ignore requests to clear D16-D31 if they don't exist */
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if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
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topreg = 31;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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/* Zero the Sregs from btmreg to topreg inclusive. */
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zero = tcg_const_i64(tcg_ctx, 0);
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if (btmreg & 1) {
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write_neon_element64(s, zero, btmreg >> 1, 1, MO_32);
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btmreg++;
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}
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for (; btmreg + 1 <= topreg; btmreg += 2) {
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write_neon_element64(s, zero, btmreg >> 1, 0, MO_64);
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}
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if (btmreg == topreg) {
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write_neon_element64(s, zero, btmreg >> 1, 0, MO_32);
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btmreg++;
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}
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assert(btmreg == topreg + 1);
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/* TODO: when MVE is implemented, zero VPR here */
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return true;
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}
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static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
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{
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/*
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@ -93,6 +93,16 @@ void arm_translate_init(struct uc_struct *uc)
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a64_translate_init(uc);
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}
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/* Generate a label used for skipping this instruction */
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static void arm_gen_condlabel(DisasContext *s)
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{
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if (!s->condjmp) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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s->condlabel = gen_new_label(tcg_ctx);
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s->condjmp = 1;
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}
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}
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/* Flags for the disas_set_da_iss info argument:
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* lower bits hold the Rt register number, higher bits are flags.
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*/
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@ -1273,6 +1283,9 @@ static void write_neon_element64(DisasContext *s, TCGv_i64 src, int reg, int ele
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long off = neon_element_offset(reg, ele, memop);
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switch (memop) {
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case MO_32:
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tcg_gen_st32_i64(tcg_ctx, src, tcg_ctx->cpu_env, off);
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break;
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case MO_64:
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tcg_gen_st_i64(tcg_ctx, src, tcg_ctx->cpu_env, off);
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break;
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@ -5236,17 +5249,6 @@ static void gen_srs(DisasContext *s,
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s->base.is_jmp = DISAS_UPDATE_EXIT;
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}
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/* Generate a label used for skipping this instruction */
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static void arm_gen_condlabel(DisasContext *s)
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{
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if (!s->condjmp) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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s->condlabel = gen_new_label(tcg_ctx);
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s->condjmp = 1;
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}
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}
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/* Skip this instruction if the ARM condition is false */
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static void arm_skip_unless(DisasContext *s, uint32_t cond)
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{
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