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target/arm: Implement the SUBP instruction

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Backports commit dad3015f55f8d48f84f0eae36021a9c6f9587e57 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 14:45:58 -05:00 committed by Lioncash
parent 13fd83fcc9
commit 43ea7aa828
1 changed files with 22 additions and 2 deletions
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24
qemu/target/arm/translate-a64.c
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@ -5538,19 +5538,39 @@ static void handle_crc32(DisasContext *s,
static void disas_data_proc_2src(DisasContext *s, uint32_t insn) static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned int sf, rm, opcode, rn, rd; unsigned int sf, rm, opcode, rn, rd, setflag;
sf = extract32(insn, 31, 1); sf = extract32(insn, 31, 1);
setflag = extract32(insn, 29, 1);
rm = extract32(insn, 16, 5); rm = extract32(insn, 16, 5);
opcode = extract32(insn, 10, 6); opcode = extract32(insn, 10, 6);
rn = extract32(insn, 5, 5); rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5); rd = extract32(insn, 0, 5);
if (extract32(insn, 29, 1)) { if (setflag && opcode != 0) {
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
switch (opcode) { switch (opcode) {
case 0: /* SUBP(S) */
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
goto do_unallocated;
} else {
TCGv_i64 tcg_n, tcg_m, tcg_d;
tcg_n = read_cpu_reg_sp(s, rn, true);
tcg_m = read_cpu_reg_sp(s, rm, true);
tcg_gen_sextract_i64(tcg_ctx, tcg_n, tcg_n, 0, 56);
tcg_gen_sextract_i64(tcg_ctx, tcg_m, tcg_m, 0, 56);
tcg_d = cpu_reg(s, rd);
if (setflag) {
gen_sub_CC(s, true, tcg_d, tcg_n, tcg_m);
} else {
tcg_gen_sub_i64(tcg_ctx, tcg_d, tcg_n, tcg_m);
}
}
break;
case 2: /* UDIV */ case 2: /* UDIV */
handle_div(s, false, sf, rm, rn, rd); handle_div(s, false, sf, rm, rn, rd);
break; break;