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i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR

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Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.

At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.

Backports commit 3fc7c73139d2d38ae80c3b0bc963b1ac1555924c from qemu
This commit is contained in:
Robert Hoo 2018-08-17 14:27:27 -04:00 committed by Lioncash
parent b3fccc4841
commit 44e0a97e0b
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 3 additions and 1 deletions
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3
qemu/target/i386/cpu.c
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@ -858,12 +858,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "spec-ctrl", NULL,
NULL, NULL, NULL, "ssbd",
NULL, "arch-capabilities", NULL, "ssbd",
},
7,
true, 0,
R_EDX,
TCG_7_0_EDX_FEATURES,
CPUID_7_0_EDX_ARCH_CAPABILITIES,
},
/* Feature names that are already defined on feature_name[] but
* are set on CPUID[8000_0001].EDX on AMD CPUs don't have their

1
qemu/target/i386/cpu.h
View file

@ -668,6 +668,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
#define KVM_HINTS_DEDICATED (1U << 0)