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target/arm: Simplify UMAAL

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Since all of the inputs and outputs are i32, dispense with
the intermediate promotion to i64 and use tcg_gen_mulu2_i32
and tcg_gen_add2_i32.

Backports commit 2409d56454f0d028619fb1002eda86bf240906dd from qemu
This commit is contained in:
Richard Henderson 2019-11-19 13:42:05 -05:00 committed by Lioncash
parent 5e5ae4c0d0
commit 45566b2780
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 23 deletions
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35
qemu/target/arm/translate.c
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@ -7493,22 +7493,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
store_reg(s, rhigh, tmp); store_reg(s, rhigh, tmp);
} }
/* load a 32-bit value from a register and perform a 64-bit accumulate. */
static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 tmp;
TCGv_i32 tmp2;
/* Load value and extend to 64 bits. */
tmp = tcg_temp_new_i64(tcg_ctx);
tmp2 = load_reg(s, rlow);
tcg_gen_extu_i32_i64(tcg_ctx, tmp, tmp2);
tcg_temp_free_i32(tcg_ctx, tmp2);
tcg_gen_add_i64(tcg_ctx, val, val, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
}
/* load and add a 64-bit value from a register pair. */ /* load and add a 64-bit value from a register pair. */
static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
{ {
@ -8339,8 +8323,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a)
static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 t0, t1; TCGv_i32 t0, t1, t2, zero;
TCGv_i64 t64;
if (s->thumb if (s->thumb
? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
@ -8350,11 +8333,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
t0 = load_reg(s, a->rm); t0 = load_reg(s, a->rm);
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
t64 = gen_mulu_i64_i32(s, t0, t1); tcg_gen_mulu2_i32(tcg_ctx, t0, t1, t0, t1);
gen_addq_lo(s, t64, a->ra); zero = tcg_const_i32(tcg_ctx, 0);
gen_addq_lo(s, t64, a->rd); t2 = load_reg(s, a->ra);
gen_storeq_reg(s, a->ra, a->rd, t64); tcg_gen_add2_i32(tcg_ctx, t0, t1, t0, t1, t2, zero);
tcg_temp_free_i64(tcg_ctx, t64); tcg_temp_free_i32(tcg_ctx, t2);
t2 = load_reg(s, a->rd);
tcg_gen_add2_i32(tcg_ctx, t0, t1, t0, t1, t2, zero);
tcg_temp_free_i32(tcg_ctx, t2);
tcg_temp_free_i32(tcg_ctx, zero);
store_reg(s, a->ra, t0);
store_reg(s, a->rd, t1);
return true; return true;
} }