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https://github.com/yuzu-emu/unicorn.git
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target/arm: Implement SVE Index Generation Group
Backports commit 9a56c9c3a955b77fe436beef7ac03c76a65fa32d from qemu
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390bd68287
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@ -3346,6 +3346,10 @@
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#define helper_sve_fneg_d helper_sve_fneg_d_aarch64
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#define helper_sve_fneg_h helper_sve_fneg_h_aarch64
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#define helper_sve_fneg_s helper_sve_fneg_s_aarch64
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#define helper_sve_index_b helper_sve_index_b_aarch64
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#define helper_sve_index_d helper_sve_index_d_aarch64
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#define helper_sve_index_h helper_sve_index_h_aarch64
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#define helper_sve_index_s helper_sve_index_s_aarch64
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#define helper_sve_lsl_zpzi_b helper_sve_lsl_zpzi_b_aarch64
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#define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64
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#define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64
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@ -3346,6 +3346,10 @@
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#define helper_sve_fneg_d helper_sve_fneg_d_aarch64eb
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#define helper_sve_fneg_h helper_sve_fneg_h_aarch64eb
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#define helper_sve_fneg_s helper_sve_fneg_s_aarch64eb
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#define helper_sve_index_b helper_sve_index_b_aarch64eb
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#define helper_sve_index_d helper_sve_index_d_aarch64eb
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#define helper_sve_index_h helper_sve_index_h_aarch64eb
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#define helper_sve_index_s helper_sve_index_s_aarch64eb
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#define helper_sve_lsl_zpzi_b helper_sve_lsl_zpzi_b_aarch64eb
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#define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64eb
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#define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64eb
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@ -3367,6 +3367,10 @@ aarch64_symbols = (
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'helper_sve_fneg_d',
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'helper_sve_fneg_h',
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'helper_sve_fneg_s',
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'helper_sve_index_b',
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'helper_sve_index_d',
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'helper_sve_index_h',
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'helper_sve_index_s',
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'helper_sve_lsl_zpzi_b',
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'helper_sve_lsl_zpzi_d',
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'helper_sve_lsl_zpzi_h',
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@ -363,6 +363,11 @@ DEF_HELPER_FLAGS_6(sve_mls_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_6(sve_mls_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_index_b, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
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DEF_HELPER_FLAGS_4(sve_index_h, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
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DEF_HELPER_FLAGS_4(sve_index_s, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
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DEF_HELPER_FLAGS_4(sve_index_d, TCG_CALL_NO_RWG, void, ptr, i64, i64, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -224,6 +224,20 @@ ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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### SVE Index Generation Group
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# SVE index generation (immediate start, immediate increment)
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INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
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# SVE index generation (immediate start, register increment)
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INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
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# SVE index generation (register start, immediate increment)
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INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
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# SVE index generation (register start, register increment)
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INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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@ -991,3 +991,43 @@ DO_ZPZZZ_D(sve_mls_d, uint64_t, DO_MLS)
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#undef DO_MLS
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#undef DO_ZPZZZ
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#undef DO_ZPZZZ_D
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void HELPER(sve_index_b)(void *vd, uint32_t start,
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uint32_t incr, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc);
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uint8_t *d = vd;
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for (i = 0; i < opr_sz; i += 1) {
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d[H1(i)] = start + i * incr;
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}
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}
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void HELPER(sve_index_h)(void *vd, uint32_t start,
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uint32_t incr, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 2;
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uint16_t *d = vd;
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for (i = 0; i < opr_sz; i += 1) {
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d[H2(i)] = start + i * incr;
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}
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}
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void HELPER(sve_index_s)(void *vd, uint32_t start,
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uint32_t incr, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 4;
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uint32_t *d = vd;
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for (i = 0; i < opr_sz; i += 1) {
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d[H4(i)] = start + i * incr;
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}
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}
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void HELPER(sve_index_d)(void *vd, uint64_t start,
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uint64_t incr, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = start + i * incr;
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}
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}
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@ -713,6 +713,89 @@ DO_ZPZZZ(MLS, mls)
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#undef DO_ZPZZZ
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/*
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*** SVE Index Generation Group
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*/
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static void do_index(DisasContext *s, int esz, int rd,
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TCGv_i64 start, TCGv_i64 incr)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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TCGv_i32 desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
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TCGv_ptr t_zd = tcg_temp_new_ptr(tcg_ctx);
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tcg_gen_addi_ptr(tcg_ctx, t_zd, tcg_ctx->cpu_env, vec_full_reg_offset(s, rd));
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if (esz == 3) {
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gen_helper_sve_index_d(tcg_ctx, t_zd, start, incr, desc);
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} else {
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typedef void index_fn(TCGContext *, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
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static index_fn * const fns[3] = {
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gen_helper_sve_index_b,
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gen_helper_sve_index_h,
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gen_helper_sve_index_s,
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};
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TCGv_i32 s32 = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 i32 = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_extrl_i64_i32(tcg_ctx, s32, start);
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tcg_gen_extrl_i64_i32(tcg_ctx, i32, incr);
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fns[esz](tcg_ctx, t_zd, s32, i32, desc);
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tcg_temp_free_i32(tcg_ctx, s32);
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tcg_temp_free_i32(tcg_ctx, i32);
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}
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tcg_temp_free_ptr(tcg_ctx, t_zd);
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tcg_temp_free_i32(tcg_ctx, desc);
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}
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static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 start = tcg_const_i64(tcg_ctx, a->imm1);
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TCGv_i64 incr = tcg_const_i64(tcg_ctx, a->imm2);
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do_index(s, a->esz, a->rd, start, incr);
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tcg_temp_free_i64(tcg_ctx, start);
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tcg_temp_free_i64(tcg_ctx, incr);
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}
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return true;
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}
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static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 start = tcg_const_i64(tcg_ctx, a->imm);
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TCGv_i64 incr = cpu_reg(s, a->rm);
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do_index(s, a->esz, a->rd, start, incr);
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tcg_temp_free_i64(tcg_ctx, start);
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}
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return true;
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}
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static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 start = cpu_reg(s, a->rn);
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TCGv_i64 incr = tcg_const_i64(tcg_ctx, a->imm);
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do_index(s, a->esz, a->rd, start, incr);
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tcg_temp_free_i64(tcg_ctx, incr);
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}
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return true;
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}
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static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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TCGv_i64 start = cpu_reg(s, a->rn);
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TCGv_i64 incr = cpu_reg(s, a->rm);
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do_index(s, a->esz, a->rd, start, incr);
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}
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return true;
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}
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/*
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*** SVE Predicate Logical Operations Group
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*/
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