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target/arm: Add set/clear_pstate_bits, share gen_ss_advance

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We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Backports commit 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 from qemu
This commit is contained in:
Richard Henderson 2019-03-05 22:48:31 -05:00 committed by Lioncash
parent 60742608f5
commit 45c297c99b
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
19 changed files with 37 additions and 45 deletions
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1
qemu/aarch64.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_aarch64
#define helper_be_stq_mmu helper_be_stq_mmu_aarch64
#define helper_be_stw_mmu helper_be_stw_mmu_aarch64
#define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64
#define helper_clrsb_i32 helper_clrsb_i32_aarch64
#define helper_clrsb_i64 helper_clrsb_i64_aarch64
#define helper_clz_i32 helper_clz_i32_aarch64

1
qemu/aarch64eb.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_aarch64eb
#define helper_be_stq_mmu helper_be_stq_mmu_aarch64eb
#define helper_be_stw_mmu helper_be_stw_mmu_aarch64eb
#define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64eb
#define helper_clrsb_i32 helper_clrsb_i32_aarch64eb
#define helper_clrsb_i64 helper_clrsb_i64_aarch64eb
#define helper_clz_i32 helper_clz_i32_aarch64eb

1
qemu/arm.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_arm
#define helper_be_stq_mmu helper_be_stq_mmu_arm
#define helper_be_stw_mmu helper_be_stw_mmu_arm
#define helper_clear_pstate_ss helper_clear_pstate_ss_arm
#define helper_clrsb_i32 helper_clrsb_i32_arm
#define helper_clrsb_i64 helper_clrsb_i64_arm
#define helper_clz_i32 helper_clz_i32_arm

1
qemu/armeb.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_armeb
#define helper_be_stq_mmu helper_be_stq_mmu_armeb
#define helper_be_stw_mmu helper_be_stw_mmu_armeb
#define helper_clear_pstate_ss helper_clear_pstate_ss_armeb
#define helper_clrsb_i32 helper_clrsb_i32_armeb
#define helper_clrsb_i64 helper_clrsb_i64_armeb
#define helper_clz_i32 helper_clz_i32_armeb

1
qemu/header_gen.py
View file

@ -1070,7 +1070,6 @@ symbols = (
'helper_be_stl_mmu',
'helper_be_stq_mmu',
'helper_be_stw_mmu',
'helper_clear_pstate_ss',
'helper_clrsb_i32',
'helper_clrsb_i64',
'helper_clz_i32',

1
qemu/m68k.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_m68k
#define helper_be_stq_mmu helper_be_stq_mmu_m68k
#define helper_be_stw_mmu helper_be_stw_mmu_m68k
#define helper_clear_pstate_ss helper_clear_pstate_ss_m68k
#define helper_clrsb_i32 helper_clrsb_i32_m68k
#define helper_clrsb_i64 helper_clrsb_i64_m68k
#define helper_clz_i32 helper_clz_i32_m68k

1
qemu/mips.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_mips
#define helper_be_stq_mmu helper_be_stq_mmu_mips
#define helper_be_stw_mmu helper_be_stw_mmu_mips
#define helper_clear_pstate_ss helper_clear_pstate_ss_mips
#define helper_clrsb_i32 helper_clrsb_i32_mips
#define helper_clrsb_i64 helper_clrsb_i64_mips
#define helper_clz_i32 helper_clz_i32_mips

1
qemu/mips64.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_mips64
#define helper_be_stq_mmu helper_be_stq_mmu_mips64
#define helper_be_stw_mmu helper_be_stw_mmu_mips64
#define helper_clear_pstate_ss helper_clear_pstate_ss_mips64
#define helper_clrsb_i32 helper_clrsb_i32_mips64
#define helper_clrsb_i64 helper_clrsb_i64_mips64
#define helper_clz_i32 helper_clz_i32_mips64

1
qemu/mips64el.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_mips64el
#define helper_be_stq_mmu helper_be_stq_mmu_mips64el
#define helper_be_stw_mmu helper_be_stw_mmu_mips64el
#define helper_clear_pstate_ss helper_clear_pstate_ss_mips64el
#define helper_clrsb_i32 helper_clrsb_i32_mips64el
#define helper_clrsb_i64 helper_clrsb_i64_mips64el
#define helper_clz_i32 helper_clz_i32_mips64el

1
qemu/mipsel.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_mipsel
#define helper_be_stq_mmu helper_be_stq_mmu_mipsel
#define helper_be_stw_mmu helper_be_stw_mmu_mipsel
#define helper_clear_pstate_ss helper_clear_pstate_ss_mipsel
#define helper_clrsb_i32 helper_clrsb_i32_mipsel
#define helper_clrsb_i64 helper_clrsb_i64_mipsel
#define helper_clz_i32 helper_clz_i32_mipsel

1
qemu/powerpc.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_powerpc
#define helper_be_stq_mmu helper_be_stq_mmu_powerpc
#define helper_be_stw_mmu helper_be_stw_mmu_powerpc
#define helper_clear_pstate_ss helper_clear_pstate_ss_powerpc
#define helper_clrsb_i32 helper_clrsb_i32_powerpc
#define helper_clrsb_i64 helper_clrsb_i64_powerpc
#define helper_clz_i32 helper_clz_i32_powerpc

1
qemu/sparc.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_sparc
#define helper_be_stq_mmu helper_be_stq_mmu_sparc
#define helper_be_stw_mmu helper_be_stw_mmu_sparc
#define helper_clear_pstate_ss helper_clear_pstate_ss_sparc
#define helper_clrsb_i32 helper_clrsb_i32_sparc
#define helper_clrsb_i64 helper_clrsb_i64_sparc
#define helper_clz_i32 helper_clz_i32_sparc

1
qemu/sparc64.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_sparc64
#define helper_be_stq_mmu helper_be_stq_mmu_sparc64
#define helper_be_stw_mmu helper_be_stw_mmu_sparc64
#define helper_clear_pstate_ss helper_clear_pstate_ss_sparc64
#define helper_clrsb_i32 helper_clrsb_i32_sparc64
#define helper_clrsb_i64 helper_clrsb_i64_sparc64
#define helper_clz_i32 helper_clz_i32_sparc64

2
qemu/target/arm/helper.h
View file

@ -79,8 +79,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
DEF_HELPER_1(clear_pstate_ss, void, env)
DEF_HELPER_2(get_r13_banked, i32, env, i32)
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)

5
qemu/target/arm/op_helper.c
View file

@ -841,11 +841,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
return ri->readfn(env, ri);
}
void HELPER(clear_pstate_ss)(CPUARMState *env)
{
env->pstate &= ~PSTATE_SS;
}
void HELPER(pre_hvc)(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);

12
qemu/target/arm/translate-a64.c
View file

@ -448,18 +448,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
s->base.is_jmp = DISAS_NORETURN;
}
static void gen_ss_advance(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
/* If the singlestep state is Active-not-pending, advance to
* Active-pending.
*/
if (s->ss_active) {
s->pstate_ss = 0;
gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env);
}
}
static void gen_step_complete_exception(DisasContext *s)
{
/* We just completed step of an insn. Move from Active-not-pending

12
qemu/target/arm/translate.c
View file

@ -299,18 +299,6 @@ static void gen_exception(DisasContext *s, int excp, uint32_t syndrome, uint32_t
tcg_temp_free_i32(tcg_ctx, tcg_excp);
}
static void gen_ss_advance(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
/* If the singlestep state is Active-not-pending, advance to
* Active-pending.
*/
if (s->ss_active) {
s->pstate_ss = 0;
gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env);
}
}
static void gen_step_complete_exception(DisasContext *s)
{
/* We just completed step of an insn. Move from Active-not-pending

37
qemu/target/arm/translate.h
View file

@ -202,6 +202,43 @@ static inline TCGv_i32 get_ahp_flag(DisasContext *s)
return ret;
}
/* Set bits within PSTATE. */
static inline void set_pstate_bits(DisasContext *s, uint32_t bits)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 p = tcg_temp_new_i32(tcg_ctx);
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(tcg_ctx, p, p, bits);
tcg_gen_st_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(tcg_ctx, p);
}
/* Clear bits within PSTATE. */
static inline void clear_pstate_bits(DisasContext *s, uint32_t bits)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 p = tcg_temp_new_i32(tcg_ctx);
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(tcg_ctx, p, p, ~bits);
tcg_gen_st_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(tcg_ctx, p);
}
/* If the singlestep state is Active-not-pending, advance to Active-pending. */
static inline void gen_ss_advance(DisasContext *s)
{
if (s->ss_active) {
s->pstate_ss = 0;
clear_pstate_bits(s, PSTATE_SS);
}
}
/* Vector operations shared between ARM and AArch64. */
extern const GVecGen3 bsl_op;
extern const GVecGen3 bit_op;

1
qemu/x86_64.h
View file

@ -1064,7 +1064,6 @@
#define helper_be_stl_mmu helper_be_stl_mmu_x86_64
#define helper_be_stq_mmu helper_be_stq_mmu_x86_64
#define helper_be_stw_mmu helper_be_stw_mmu_x86_64
#define helper_clear_pstate_ss helper_clear_pstate_ss_x86_64
#define helper_clrsb_i32 helper_clrsb_i32_x86_64
#define helper_clrsb_i64 helper_clrsb_i64_x86_64
#define helper_clz_i32 helper_clz_i32_x86_64