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target/mips: Clean up handling of CP0 register 0

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Clean up handling of CP0 register 0.

Backports commit 1b142da5f82a8fcdc7783a418592de654d5c6052 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 22:25:12 -05:00 committed by Lioncash
parent effccae2d9
commit 47adeabf87
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 23 additions and 20 deletions
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3
qemu/target/mips/cpu.h
View file

@ -276,6 +276,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
#define CP0_REG00__MVPCONTROL 1
#define CP0_REG00__MVPCONF0 2
#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */

40
qemu/target/mips/translate.c
View file

@ -6896,26 +6896,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
case 0:
case CP0_REG00__INDEX:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
case 1:
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPControl";
break;
case 2:
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPConf0";
break;
case 3:
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPConf1";
break;
case 4:
case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@ -7653,26 +7653,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
case 0:
case CP0_REG00__INDEX:
gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Index";
break;
case 1:
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "MVPControl";
break;
case 2:
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
case 3:
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
case 4:
case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@ -8394,26 +8394,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
case 0:
case CP0_REG00__INDEX:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
case 1:
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPControl";
break;
case 2:
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPConf0";
break;
case 3:
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "MVPConf1";
break;
case 4:
case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@ -9106,26 +9106,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
case 0:
case CP0_REG00__INDEX:
gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Index";
break;
case 1:
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "MVPControl";
break;
case 2:
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
case 3:
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
case 4:
case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";