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target/riscv: Allow setting mstatus virtulisation bits

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Backports commit 1f0419cb0475eebdbefea67483e85287f3af07a7 from qemu
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Alistair Francis 2019-05-28 19:16:31 -04:00 committed by Lioncash
parent c64f57c360
commit 47e4e047bc
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 8 deletions
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16
qemu/target/riscv/csr.c
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@ -297,11 +297,10 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
{ {
target_ulong mstatus = env->mstatus; target_ulong mstatus = env->mstatus;
target_ulong mask = 0; target_ulong mask = 0;
target_ulong mpp = get_field(val, MSTATUS_MPP);
/* flush tlb on mstatus fields that affect VM */ /* flush tlb on mstatus fields that affect VM */
if (env->priv_ver <= PRIV_VERSION_1_09_1) { if (env->priv_ver <= PRIV_VERSION_1_09_1) {
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
tlb_flush(CPU(riscv_env_get_cpu(env))); tlb_flush(CPU(riscv_env_get_cpu(env)));
} }
@ -320,13 +319,14 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW; MSTATUS_TW;
}
/* silenty discard mstatus.mpp writes for unsupported modes */ #if defined(TARGET_RISCV64)
if (mpp == PRV_H || /*
(!riscv_has_ext(env, RVS) && mpp == PRV_S) || * RV32: MPV and MTL are not in mstatus. The current plan is to
(!riscv_has_ext(env, RVU) && mpp == PRV_U)) { * add them to mstatush. For now, we just don't support it.
mask &= ~MSTATUS_MPP; */
mask |= MSTATUS_MPP | MSTATUS_MPV;
#endif
} }
mstatus = (mstatus & ~mask) | (val & mask); mstatus = (mstatus & ~mask) | (val & mask);