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target-arm: Fix broken SCTLR_EL3 reset

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The SCTLR_EL3 cpreg definition was implicitly resetting the
register state to 0, which is both wrong and clashes with
the reset done via the SCTLR definition (since sctlr[3]
is unioned with sctlr_s). This went unnoticed until recently,
when an unrelated change (commit a903c449b41f105aa) happened to
perturb the order of enumeration through the cpregs hashtable for
reset such that the erroneous reset happened after the correct one
rather than before it. Fix this by marking SCTLR_EL3 as an alias,
so its reset is left up to the AArch32 view.

Backports commit e46e1a74ef482f1ef773e750df9654ef4442ca29 from qemu
This commit is contained in:
Peter Maydell 2018-02-14 15:08:44 -05:00 committed by Lioncash
parent 6279dfc113
commit 484a9cc21b
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
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3
qemu/target-arm/helper.c
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@ -2369,7 +2369,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "MVBAR", 15,12,0, 0,0,1, 0,0, { "MVBAR", 15,12,0, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0}, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
NULL, NULL, vbar_write }, NULL, NULL, vbar_write },
{ "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,0, { "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, /* reset handled by AArch32 view */
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0}, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},
NULL, NULL, sctlr_write, NULL, raw_write, }, NULL, NULL, sctlr_write, NULL, raw_write, },
{ "TTBR0_EL3", 0,2,0, 3,6,0, ARM_CP_STATE_AA64,0, { "TTBR0_EL3", 0,2,0, 3,6,0, ARM_CP_STATE_AA64,0,