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https://github.com/yuzu-emu/unicorn.git
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target/mips: Add emulation of some common nanoMIPS 32-bit instructions
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC, ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions. Backports commit c0280983034627a336248409711e969eb2ea8325 from qemu
This commit is contained in:
Yongbok Kim
Lioncash
parent
6b5dbbf6a3
commit
48d61aee0b
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@ -16975,6 +16975,274 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
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}
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}
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static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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uint16_t insn;
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uint32_t op;
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int rt, rs;
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int offset;
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int imm;
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insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
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ctx->opcode = (ctx->opcode << 16) | insn;
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rt = extract32(ctx->opcode, 21, 5);
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rs = extract32(ctx->opcode, 16, 5);
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op = extract32(ctx->opcode, 26, 6);
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switch (op) {
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case NM_P_ADDIU:
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if (rt == 0) {
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/* P.RI */
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switch (extract32(ctx->opcode, 19, 2)) {
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case NM_SIGRIE:
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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case NM_P_SYSCALL:
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if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
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generate_exception_end(ctx, EXCP_SYSCALL);
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} else {
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generate_exception_end(ctx, EXCP_RI);
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}
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break;
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case NM_BREAK:
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generate_exception_end(ctx, EXCP_BREAK);
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break;
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case NM_SDBBP:
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// Unicorn: Commented out
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/*if (is_uhi(extract32(ctx->opcode, 0, 19))) {
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gen_helper_do_semihosting(cpu_env);
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} else*/ {
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if (ctx->hflags & MIPS_HFLAG_SBRI) {
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generate_exception_end(ctx, EXCP_RI);
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} else {
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generate_exception_end(ctx, EXCP_DBp);
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}
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}
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break;
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}
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} else {
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/* NM_ADDIU */
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imm = extract32(ctx->opcode, 0, 16);
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if (rs != 0) {
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tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rs], imm);
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} else {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], imm);
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}
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tcg_gen_ext32s_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rt]);
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}
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break;
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case NM_ADDIUPC:
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if (rt != 0) {
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offset = sextract32(ctx->opcode, 0, 1) << 21 |
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extract32(ctx->opcode, 1, 20) << 1;
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target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], addr);
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}
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break;
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case NM_POOL32A:
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break;
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case NM_P_GP_W:
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switch (ctx->opcode & 0x03) {
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case NM_ADDIUGP_W:
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if (rt != 0) {
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offset = extract32(ctx->opcode, 0, 21);
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gen_op_addr_addi(ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[28], offset);
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}
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break;
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case NM_LWGP:
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gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
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break;
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case NM_SWGP:
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gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P48I:
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return 6;
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case NM_P_U12:
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switch (extract32(ctx->opcode, 12, 4)) {
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case NM_ORI:
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gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12));
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break;
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case NM_XORI:
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gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12));
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break;
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case NM_ANDI:
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gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12));
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break;
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case NM_P_SR:
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switch (extract32(ctx->opcode, 20, 1)) {
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case NM_PP_SR:
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switch (ctx->opcode & 3) {
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case NM_SAVE:
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gen_save(ctx, rt, extract32(ctx->opcode, 16, 4),
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extract32(ctx->opcode, 2, 1),
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extract32(ctx->opcode, 3, 9) << 3);
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break;
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case NM_RESTORE:
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case NM_RESTORE_JRC:
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gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4),
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extract32(ctx->opcode, 2, 1),
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extract32(ctx->opcode, 3, 9) << 3);
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if ((ctx->opcode & 3) == NM_RESTORE_JRC) {
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gen_compute_branch_nm(ctx, OPC_JR, 2, 31, 0, 0);
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_SR_F:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_SLTI:
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gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12));
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break;
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case NM_SLTIU:
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gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12));
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break;
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case NM_SEQI:
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{
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TCGv t0 = tcg_temp_new(tcg_ctx);
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imm = extract32(ctx->opcode, 0, 12);
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gen_load_gpr(ctx, t0, rs);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, t0, t0, imm);
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gen_store_gpr(tcg_ctx, t0, rt);
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case NM_ADDIUNEG:
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imm = (int16_t) extract32(ctx->opcode, 0, 12);
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gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);
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break;
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case NM_P_SHIFT:
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{
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int shift = extract32(ctx->opcode, 0, 5);
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switch (extract32(ctx->opcode, 5, 4)) {
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case NM_P_SLL:
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if (rt == 0 && shift == 0) {
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/* NOP */
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} else if (rt == 0 && shift == 3) {
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/* EHB - treat as NOP */
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} else if (rt == 0 && shift == 5) {
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/* PAUSE - treat as NOP */
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} else if (rt == 0 && shift == 6) {
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/* SYNC */
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gen_sync(tcg_ctx, extract32(ctx->opcode, 16, 5));
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} else {
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/* SLL */
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gen_shift_imm(ctx, OPC_SLL, rt, rs,
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extract32(ctx->opcode, 0, 5));
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}
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break;
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case NM_SRL:
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gen_shift_imm(ctx, OPC_SRL, rt, rs,
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extract32(ctx->opcode, 0, 5));
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break;
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case NM_SRA:
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gen_shift_imm(ctx, OPC_SRA, rt, rs,
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extract32(ctx->opcode, 0, 5));
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break;
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case NM_ROTR:
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gen_shift_imm(ctx, OPC_ROTR, rt, rs,
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extract32(ctx->opcode, 0, 5));
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break;
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}
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}
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break;
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case NM_P_ROTX:
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break;
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case NM_P_INS:
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switch (((ctx->opcode >> 10) & 2) |
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(extract32(ctx->opcode, 5, 1))) {
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case NM_INS:
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gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5),
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extract32(ctx->opcode, 6, 5));
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_EXT:
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switch (((ctx->opcode >> 10) & 2) |
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(extract32(ctx->opcode, 5, 1))) {
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case NM_EXT:
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gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),
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extract32(ctx->opcode, 6, 5));
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_POOL32F:
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break;
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case NM_POOL32S:
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break;
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case NM_P_LUI:
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switch (extract32(ctx->opcode, 1, 1)) {
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case NM_LUI:
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if (rt != 0) {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt],
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sextract32(ctx->opcode, 0, 1) << 31 |
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extract32(ctx->opcode, 2, 10) << 21 |
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extract32(ctx->opcode, 12, 9) << 12);
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}
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break;
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case NM_ALUIPC:
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if (rt != 0) {
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offset = sextract32(ctx->opcode, 0, 1) << 31 |
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extract32(ctx->opcode, 2, 10) << 21 |
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extract32(ctx->opcode, 12, 9) << 12;
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target_long addr;
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addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset);
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], addr);
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}
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break;
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}
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break;
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case NM_P_GP_BH:
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break;
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case NM_P_LS_U12:
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break;
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case NM_P_LS_S9:
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break;
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case NM_MOVE_BALC:
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break;
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case NM_P_BAL:
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break;
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case NM_P_J:
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break;
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case NM_P_BR1:
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break;
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case NM_P_BR2:
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break;
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case NM_P_BRI:
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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return 4;
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}
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static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -17287,7 +17555,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_MOVEPREV:
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break;
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default:
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break;
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return decode_nanomips_32_48_opc(env, ctx);
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}
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return 2;
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