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target/riscv: Add the privledge spec version 1.11.0

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Add support for the ratified RISC-V privledge spec.

Backports commit 6729dbbd420696fcf69cf2c86bdfc66e072058ce from qemu
This commit is contained in:
Alistair Francis 2019-08-08 17:03:29 -04:00 committed by Lioncash
parent 9241c2c842
commit 4934db3de6
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 2 additions and 1 deletions
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1
qemu/target/riscv/cpu.h
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@ -85,6 +85,7 @@ enum {
#define USER_VERSION_2_02_0 0x00020200
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1

2
qemu/target/riscv/insn_trans/trans_privileged.inc.c
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@ -93,7 +93,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;