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target/mips: Tidy control flow in mips_cpu_handle_mmu_fault
Since the only non-negative TLBRET_* value is TLBRET_MATCH, the subsequent test for ret < 0 is useless. Use early return to allow subsequent blocks to be unindented. Backports commit e38f4eb63020075432cb77bf48398187809cf4a3 from qemu
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@ -902,11 +902,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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return 0;
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} else if (ret < 0)
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}
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#endif
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{
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(TARGET_MIPS64)
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#if !defined(TARGET_MIPS64)
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if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
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if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
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/*
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/*
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@ -925,18 +922,14 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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return 0;
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return ret;
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}
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}
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}
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}
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}
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}
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#endif
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#endif
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#endif
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#endif
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raise_mmu_exception(env, address, rw, ret);
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raise_mmu_exception(env, address, rw, ret);
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ret = 1;
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return 1;
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}
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return ret;
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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