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tcg: Remove tcg_regset_clear

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Backports commit ccb1bb66ea2a42e773bfa04178d8b383ff86d4d8 from qemu
This commit is contained in:
Richard Henderson 2018-03-04 23:23:28 -05:00 committed by Lioncash
parent 7b68a8f0ca
commit 49d09d6888
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GPG key ID: 4E3C3CC1031BA9C7
9 changed files with 13 additions and 15 deletions
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2
qemu/tcg/aarch64/tcg-target.inc.c
View file

@ -1955,7 +1955,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_X16) | (1 << TCG_REG_X17) | (1 << TCG_REG_X16) | (1 << TCG_REG_X17) |
(1 << TCG_REG_X18) | (1 << TCG_REG_X30)); (1 << TCG_REG_X18) | (1 << TCG_REG_X30));
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);

2
qemu/tcg/arm/tcg-target.inc.c
View file

@ -2173,7 +2173,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_R12) | (1 << TCG_REG_R12) |
(1 << TCG_REG_R14)); (1 << TCG_REG_R14));
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);

4
qemu/tcg/i386/tcg-target.inc.c
View file

@ -2776,7 +2776,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
} }
tcg_regset_clear(s->tcg_target_call_clobber_regs); s->tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_EAX); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_EAX);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_EDX); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_EDX);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_ECX); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_ECX);
@ -2791,6 +2791,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R11); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R11);
} }
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
} }

2
qemu/tcg/mips/tcg-target.inc.c
View file

@ -2644,7 +2644,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_T8) | (1 << TCG_REG_T8) |
(1 << TCG_REG_T9)); (1 << TCG_REG_T9));
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */

2
qemu/tcg/ppc/tcg-target.inc.c
View file

@ -2734,7 +2734,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_R11) | (1 << TCG_REG_R11) |
(1 << TCG_REG_R12)); (1 << TCG_REG_R12));
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
#if defined(_CALL_SYSV) #if defined(_CALL_SYSV)

8
qemu/tcg/s390/tcg-target.inc.c
View file

@ -419,12 +419,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 'a': /* force R2 for division */ case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_clear(ct->u.regs); ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
break; break;
case 'b': /* force R3 for division */ case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_clear(ct->u.regs); ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
break; break;
case 'A': case 'A':
@ -2655,7 +2655,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
tcg_regset_clear(s->tcg_target_call_clobber_regs); s->tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R1); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R1);
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2);
@ -2668,7 +2668,7 @@ static void tcg_target_init(TCGContext *s)
/* The return register can be considered call-clobbered. */ /* The return register can be considered call-clobbered. */
tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14);
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
/* XXX many insns can't be used with R0, so we better avoid it for now */ /* XXX many insns can't be used with R0, so we better avoid it for now */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);

2
qemu/tcg/sparc/tcg-target.inc.c
View file

@ -1774,7 +1774,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_O5) | (1 << TCG_REG_O5) |
(1 << TCG_REG_O7)); (1 << TCG_REG_O7));
tcg_regset_clear(s->reserved_regs); s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */

5
qemu/tcg/tcg.c
View file

@ -1548,7 +1548,7 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */ /* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL); tcg_debug_assert(ct_str != NULL);
tcg_regset_clear(def->args_ct[i].u.regs); def->args_ct[i].u.regs = 0;
def->args_ct[i].ct = 0; def->args_ct[i].ct = 0;
while (*ct_str != '\0') { while (*ct_str != '\0') {
switch(*ct_str) { switch(*ct_str) {
@ -2740,9 +2740,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
tcg_out_mov(s, ts->type, reg, ts->reg); tcg_out_mov(s, ts->type, reg, ts->reg);
} }
} else { } else {
TCGRegSet arg_set; TCGRegSet arg_set = 0;
tcg_regset_clear(arg_set);
tcg_regset_set_reg(arg_set, reg); tcg_regset_set_reg(arg_set, reg);
temp_load(s, ts, arg_set, allocated_regs); temp_load(s, ts, arg_set, allocated_regs);
} }

1
qemu/tcg/tcg.h
View file

@ -189,7 +189,6 @@ typedef enum TCGOpcode {
NB_OPS, NB_OPS,
} TCGOpcode; } TCGOpcode;
#define tcg_regset_clear(d) (d) = 0
#define tcg_regset_set(d, s) (d) = (s) #define tcg_regset_set(d, s) (d) = (s)
#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
#define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)