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target/mips: Clean up handling of CP0 register 5

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Clean up handling of CP0 register 5.

Backports commit a1e76353e389f93e63bf1175c8422e5e7759662e from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 22:51:17 -05:00 committed by Lioncash
parent 11ac98331a
commit 49eeba113e
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 38 additions and 32 deletions
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6
qemu/target/mips/cpu.h
View file

@ -312,6 +312,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1
#define CP0_REG05__SEGCTL0 2
#define CP0_REG05__SEGCTL1 3
#define CP0_REG05__SEGCTL2 4
#define CP0_REG05__PWBASE 5
#define CP0_REG05__PWFIELD 6
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */

64
qemu/target/mips/translate.c
View file

@ -7081,43 +7081,43 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
case 0:
case CP0_REG05__PAGEMASK:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
case 1:
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
case 2:
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
register_name = "SegCtl0";
break;
case 3:
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
register_name = "SegCtl1";
break;
case 4:
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
register_name = "SegCtl2";
case 5:
case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case 6:
case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
case 7:
case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@ -7812,42 +7812,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
case 0:
case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PageMask";
break;
case 1:
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
case 2:
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl0";
break;
case 3:
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl1";
break;
case 4:
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl2";
break;
case 5:
case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case 6:
case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWField";
break;
case 7:
case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWSize";
@ -8553,41 +8553,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
case 0:
case CP0_REG05__PAGEMASK:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
case 1:
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
case 2:
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
case 3:
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
case 4:
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
case 5:
case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case 6:
case CP0_REG05__PWFIELD:
check_pw(ctx);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
case 7:
case CP0_REG05__PWSIZE:
check_pw(ctx);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@ -9265,41 +9265,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
case 0:
case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PageMask";
break;
case 1:
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PageGrain";
break;
case 2:
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl0";
break;
case 3:
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl1";
break;
case 4:
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "SegCtl2";
break;
case 5:
case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case 6:
case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWField";
break;
case 7:
case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "PWSize";