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target/i386: Fix andn instruction
In commit 7073fbada733c8d10992f00772c9b9299d740e9b, the `andn` instruction was implemented via `tcg_gen_andc` but passes the operands in the wrong order: - X86 defines `andn dest,src1,src2` as: dest = ~src1 & src2 - TCG defines `andc dest,src1,src2` as: dest = src1 & ~src2 The following simple test shows the issue: int main(void) { uint32_t ret = 0; __asm ( "mov $0xFF00, %%ecx\n" "mov $0x0F0F, %%eax\n" "andn %%ecx, %%eax, %%ecx\n" "mov %%ecx, %0\n" : "=r" (ret)); printf("%08X\n", ret); return 0; } This patch fixes the problem by simply swapping the order of the two last arguments in `tcg_gen_andc_tl`. Backports commit 5cd10051c2e02b7a86eae49919d6c65a87dbea46 from qemu
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@ -4363,7 +4363,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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ot = mo_64_32(s->dflag);
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gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
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tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_regs[s->vex_v], cpu_T0);
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tcg_gen_andc_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_regs[s->vex_v]);
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gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0);
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gen_op_update1_cc(tcg_ctx);
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set_cc_op(s, CC_OP_LOGICB + ot);
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