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target/mips: Add emulation of MMI instruction PCPYUD
Add emulation of MMI instruction PCPYUD. The emulation is implemented using TCG front end operations directly to achieve better performance. Backports commit fd487f83ea92d790559813c5a0a719c30ca9ecde from qemu
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@ -24590,6 +24590,46 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
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}
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}
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/*
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* PCPYUD rd, rs, rt
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*
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* Parallel Copy Upper Doubleword
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+---------+---------+---------+---------+-----------+
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* | MMI | rs | rt | rd | PCPYUD | MMI3 |
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* +-----------+---------+---------+---------+---------+-----------+
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*/
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static void gen_mmi_pcpyud(DisasContext *ctx)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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uint32_t rs, rt, rd;
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uint32_t opcode;
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opcode = ctx->opcode;
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rs = extract32(opcode, 21, 5);
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rt = extract32(opcode, 16, 5);
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rd = extract32(opcode, 11, 5);
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if (rd == 0) {
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/* nop */
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} else {
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if (rs == 0) {
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tcg_gen_movi_i64(tcg_ctx, tcg_ctx->cpu_gpr[rd], 0);
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} else {
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_gpr[rd], tcg_ctx->cpu_mmr[rs]);
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}
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if (rt == 0) {
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tcg_gen_movi_i64(tcg_ctx, tcg_ctx->cpu_mmr[rd], 0);
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} else {
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if (rd != rt) {
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tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_mmr[rd], tcg_ctx->cpu_mmr[rt]);
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}
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}
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}
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}
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#endif
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@ -27654,7 +27694,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
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case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
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case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
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case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
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case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
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case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
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case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
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case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
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@ -27664,6 +27703,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
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case MMI_OPC_3_PCPYH:
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gen_mmi_pcpyh(ctx);
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break;
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case MMI_OPC_3_PCPYUD:
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gen_mmi_pcpyud(ctx);
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break;
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default:
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MIPS_INVAL("TX79 MMI class MMI3");
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generate_exception_end(ctx, EXCP_RI);
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