mirror of
https://github.com/yuzu-emu/unicorn.git
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target/i386: [tcg] Port to DisasContextBase
Incrementally paves the way towards using the generic instruction translation loop. Backports commit 6cf147aa299e49f7794858609a1e8ef19f81c007 from qemu
This commit is contained in:
Lluís Vilanova
Lioncash
parent
ed7225e685
commit
4babc3ff64
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@ -72,6 +72,7 @@
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#include "exec/gen-icount.h"
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typedef struct DisasContext {
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DisasContextBase base;
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/* current insn context */
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int override; /* -1 if no override */
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int prefix;
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@ -79,8 +80,6 @@ typedef struct DisasContext {
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TCGMemOp dflag;
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target_ulong pc_start;
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target_ulong pc; /* pc = eip + cs_base */
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int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
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static state change (stop translation) */
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/* current block context */
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target_ulong cs_base; /* base of CS segment */
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int pe; /* protected mode */
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@ -102,12 +101,10 @@ typedef struct DisasContext {
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int cpl;
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int iopl;
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int tf; /* TF cpu flag */
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int singlestep_enabled; /* "hardware" single step enabled */
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int jmp_opt; /* use direct block chaining for direct jumps */
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int repz_opt; /* optimize jumps within repz instructions */
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int mem_index; /* select memory access functions */
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uint64_t flags; /* all execution flags */
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struct TranslationBlock *tb;
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int popl_esp_hack; /* for correct popl with esp base handling */
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int rip_offset; /* only used in x86_64, but left for simplicity */
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int cpuid_features;
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@ -2414,7 +2411,7 @@ static inline int insn_const_size(TCGMemOp ot)
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static inline bool use_goto_tb(DisasContext *s, target_ulong pc)
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{
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#ifndef CONFIG_USER_ONLY
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return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) ||
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return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) ||
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(pc & TARGET_PAGE_MASK) == (s->pc_start & TARGET_PAGE_MASK);
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#else
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return true;
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@ -2430,8 +2427,8 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
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/* jump to same page: we can use a direct jump */
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tcg_gen_goto_tb(tcg_ctx, tb_num);
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gen_jmp_im(s, eip);
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tcg_gen_exit_tb(tcg_ctx, (uintptr_t)s->tb + tb_num);
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s->is_jmp = DISAS_NORETURN;
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tcg_gen_exit_tb(tcg_ctx, (uintptr_t)s->base.tb + tb_num);
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s->base.is_jmp = DISAS_NORETURN;
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} else {
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/* jump to another page */
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gen_jr(s, tcg_ctx->cpu_tmp0);
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@ -2535,12 +2532,12 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg)
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stop as a special handling must be done to disable hardware
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interrupts for the next instruction */
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if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) {
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s->is_jmp = DISAS_TOO_MANY;
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s->base.is_jmp = DISAS_TOO_MANY;
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}
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} else {
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gen_op_movl_seg_T0_vm(tcg_ctx, seg_reg);
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if (seg_reg == R_SS) {
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s->is_jmp = DISAS_TOO_MANY;
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s->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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}
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@ -2747,7 +2744,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
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gen_update_cc_op(s);
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gen_jmp_im(s, cur_eip);
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gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, trapno));
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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/* Generate #UD for the current instruction. The assumption here is that
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@ -2786,7 +2783,7 @@ static void gen_interrupt(DisasContext *s, int intno,
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gen_jmp_im(s, cur_eip);
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gen_helper_raise_interrupt(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, intno),
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tcg_const_i32(tcg_ctx, next_eip - cur_eip));
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_debug(DisasContext *s, target_ulong cur_eip)
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@ -2796,7 +2793,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip)
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gen_update_cc_op(s);
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gen_jmp_im(s, cur_eip);
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gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_set_hflag(DisasContext *s, uint32_t mask)
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@ -2863,10 +2860,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr)
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gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);
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}
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if (s->tb->flags & HF_RF_MASK) {
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if (s->base.tb->flags & HF_RF_MASK) {
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gen_helper_reset_rf(tcg_ctx, tcg_ctx->cpu_env);
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}
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if (s->singlestep_enabled) {
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if (s->base.singlestep_enabled) {
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gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
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} else if (recheck_tf) {
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gen_helper_rechecking_single_step(tcg_ctx, tcg_ctx->cpu_env);
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@ -2882,7 +2879,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr)
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} else {
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tcg_gen_exit_tb(tcg_ctx, 0);
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}
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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static inline void
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@ -2921,7 +2918,7 @@ static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
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set_cc_op(s, CC_OP_DYNAMIC);
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if (s->jmp_opt) {
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gen_goto_tb(s, tb_num, eip);
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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} else {
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gen_jmp_im(s, eip);
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gen_eob(s);
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@ -5007,7 +5004,7 @@ static void restore_eflags(DisasContext *s, TCGContext *tcg_ctx)
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}
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*/
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/* convert one instruction. s->is_jmp is set if the translation must
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/* convert one instruction. s->base.is_jmp is set if the translation must
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be stopped. Return the next pc value */
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static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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target_ulong pc_start) // qq
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@ -5045,7 +5042,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_hlt(tcg_ctx, cpu_env, tcg_const_i32(tcg_ctx, s->pc - pc_start));
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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return s->pc;
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}
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@ -6027,7 +6024,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_movl_seg_T0(s, reg);
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gen_pop_update(s, ot);
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/* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */
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if (s->is_jmp) {
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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if (reg == R_SS) {
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s->tf = 0;
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@ -6042,7 +6039,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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ot = gen_pop_T0(s);
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gen_movl_seg_T0(s, (b >> 3) & 7);
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gen_pop_update(s, ot);
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if (s->is_jmp) {
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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}
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@ -6099,7 +6096,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
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gen_movl_seg_T0(s, reg);
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/* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */
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if (s->is_jmp) {
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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if (reg == R_SS) {
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s->tf = 0;
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@ -6311,7 +6308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_movl_seg_T0(s, op);
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/* then put the data */
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gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T1);
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if (s->is_jmp) {
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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}
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@ -7619,7 +7616,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_pause(tcg_ctx, cpu_env, tcg_const_i32(tcg_ctx, s->pc - pc_start));
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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break;
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case 0x9b: /* fwait */
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@ -7872,7 +7869,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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gen_helper_hlt(tcg_ctx, cpu_env, tcg_const_i32(tcg_ctx, s->pc - pc_start));
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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}
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break;
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case 0x100:
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@ -8055,7 +8052,7 @@ case 0x101:
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tcg_const_i32(tcg_ctx, s->aflag - 1),
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tcg_const_i32(tcg_ctx, s->pc - pc_start));
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tcg_gen_exit_tb(tcg_ctx, 0);
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s->is_jmp = DISAS_NORETURN;
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s->base.is_jmp = DISAS_NORETURN;
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break;
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case 0xd9: /* VMMCALL */
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@ -8258,12 +8255,12 @@ case 0x101:
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}
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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// Unicorn: commented out
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//gen_io_start();
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}
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gen_helper_rdtscp(tcg_ctx, cpu_env);
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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// Unicorn: commented out
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//gen_io_end();
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gen_jmp(s, s->pc - s->cs_base);
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@ -8631,7 +8628,7 @@ case 0x101:
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if (b & 2) {
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// Unicorn: if'd out
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#if 0
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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gen_io_start();
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}
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#endif
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@ -8641,7 +8638,7 @@ case 0x101:
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// Unicorn: if'd out
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#if 0
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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gen_io_end();
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}
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#endif
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@ -8650,14 +8647,14 @@ case 0x101:
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} else {
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// Unicorn: if'd out
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#if 0
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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gen_io_start();
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}
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#endif
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gen_helper_read_crN(tcg_ctx, cpu_T0, cpu_env, tcg_const_i32(tcg_ctx, reg));
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gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
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#if 0
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if (s->tb->cflags & CF_USE_ICOUNT) {
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if (s->base.tb->cflags & CF_USE_ICOUNT) {
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gen_io_end();
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}
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#endif
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@ -9154,16 +9151,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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CPUX86State *env = cs->env_ptr;
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_ptr;
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uint32_t flags;
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target_ulong pc_start;
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target_ulong cs_base;
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int num_insns = 0;
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int max_insns;
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bool block_full = false;
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/* generate intermediate code */
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pc_start = tb->pc;
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dc->base.pc_first = tb->pc;
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cs_base = tb->cs_base;
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flags = tb->flags;
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@ -9177,11 +9172,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
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dc->iopl = (flags >> IOPL_SHIFT) & 3;
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dc->tf = (flags >> TF_SHIFT) & 1;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->last_cc_op = dc->cc_op = CC_OP_DYNAMIC;
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dc->cc_op_dirty = false;
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dc->cs_base = cs_base;
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dc->tb = tb;
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dc->base.tb = tb;
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dc->popl_esp_hack = 0;
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/* select memory access functions */
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dc->mem_index = 0;
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@ -9237,7 +9232,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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// done with initializing TCG variables
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env->uc->init_tcg = true;
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pc_ptr = pc_start;
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dc->base.pc_next = dc->base.pc_first;
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// early check to see if the address of this block is the until address
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if (tb->pc == env->uc->addr_end) {
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@ -9245,11 +9240,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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gen_tb_start(tcg_ctx, tb);
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gen_jmp_im(dc, tb->pc - tb->cs_base);
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gen_helper_hlt(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, 0));
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dc->is_jmp = DISAS_NORETURN;
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dc->base.is_jmp = DISAS_NORETURN;
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goto done_generating;
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}
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dc->is_jmp = DISAS_NEXT;
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dc->base.is_jmp = DISAS_NEXT;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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@ -9260,30 +9255,30 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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// Unicorn: trace this block on request
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// Only hook this block if the previous block was not truncated due to space
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if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, pc_start)) {
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if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, dc->base.pc_first)) {
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int arg_i = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
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env->uc->block_addr = pc_start;
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env->uc->block_addr = dc->base.pc_first;
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env->uc->size_arg = arg_i + 1;
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, pc_start);
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, dc->base.pc_first);
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} else {
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env->uc->size_arg = -1;
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}
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gen_tb_start(tcg_ctx, tb);
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for(;;) {
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tcg_gen_insn_start(tcg_ctx, pc_start, dc->cc_op);
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tcg_gen_insn_start(tcg_ctx, dc->base.pc_next, dc->cc_op);
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num_insns++;
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/* If RF is set, suppress an internally generated breakpoint. */
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if (unlikely(cpu_breakpoint_test(cs, pc_ptr,
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next,
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tb->flags & HF_RF_MASK
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? BP_GDB : BP_ANY))) {
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gen_debug(dc, pc_ptr - dc->cs_base);
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gen_debug(dc, dc->base.pc_next - dc->cs_base);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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pc_ptr += 1;
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dc->base.pc_next += 1;
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goto done_generating;
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}
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// Unicorn: commented out
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@ -9292,19 +9287,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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//}
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// Unicorn: save current PC address to sync EIP
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dc->prev_pc = pc_ptr;
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pc_ptr = disas_insn(env, dc, pc_ptr);
|
||||
dc->prev_pc = dc->base.pc_next;
|
||||
dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next);
|
||||
/* stop translation if indicated */
|
||||
if (dc->is_jmp)
|
||||
if (dc->base.is_jmp) {
|
||||
break;
|
||||
}
|
||||
/* if single step mode, we generate only one instruction and
|
||||
generate an exception */
|
||||
/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
|
||||
the flag and abort the translation to give the irqs a
|
||||
change to be happen */
|
||||
if (dc->tf || dc->singlestep_enabled ||
|
||||
if (dc->tf || dc->base.singlestep_enabled ||
|
||||
(flags & HF_INHIBIT_IRQ_MASK)) {
|
||||
gen_jmp_im(dc, pc_ptr - dc->cs_base);
|
||||
gen_jmp_im(dc, dc->base.pc_next - dc->cs_base);
|
||||
gen_eob(dc);
|
||||
break;
|
||||
}
|
||||
|
|
@ -9316,18 +9312,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
|
|||
*/
|
||||
/* UNICORN: Commented out
|
||||
if (use_icount
|
||||
&& ((pc_ptr & TARGET_PAGE_MASK)
|
||||
!= ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)
|
||||
|| (pc_ptr & ~TARGET_PAGE_MASK) == 0)) {
|
||||
gen_jmp_im(dc, pc_ptr - dc->cs_base);
|
||||
&& ((dc->base.pc_next & TARGET_PAGE_MASK)
|
||||
!= ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)
|
||||
|| (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {
|
||||
gen_jmp_im(dc, dc->base.pc_next - dc->cs_base);
|
||||
gen_eob(dc);
|
||||
break;
|
||||
}*/
|
||||
/* if too long translation, stop generation too */
|
||||
if (tcg_op_buf_full(tcg_ctx) ||
|
||||
(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
|
||||
(dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) ||
|
||||
num_insns >= max_insns) {
|
||||
gen_jmp_im(dc, pc_ptr - dc->cs_base);
|
||||
gen_jmp_im(dc, dc->base.pc_next - dc->cs_base);
|
||||
gen_eob(dc);
|
||||
block_full = true;
|
||||
break;
|
||||
|
|
@ -9338,7 +9334,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
|
|||
done_generating:
|
||||
gen_tb_end(tcg_ctx, tb, num_insns);
|
||||
|
||||
tb->size = pc_ptr - pc_start;
|
||||
tb->size = dc->base.pc_next - dc->base.pc_first;
|
||||
tb->icount = num_insns;
|
||||
|
||||
env->uc->block_full = block_full;
|
||||
|
|
|
|||
Loading…
Reference in a new issue