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tcg: Use memset for large vector byte replication

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In f47db80cc07, we handled odd-sized tail clearing for
the case of hosts that have vector operations, but did
not handle the case of hosts that do not have vector ops.

This was ok until e2e7168a214b, which changed the encoding
of simd_desc such that the odd sizes are impossible.

Add memset as a tcg helper, and use that for all out-of-line
byte stores to vectors. This includes, but is not limited to,
the tail clearing operation in question.

Backports 6d3ef04893bdea3e7aa08be3cce5141902836a31
This commit is contained in:
Richard Henderson 2021-03-03 19:25:02 -05:00 committed by Lioncash
parent 6a22a7b80e
commit 4ccadaf6cf
3 changed files with 46 additions and 0 deletions
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11
qemu/accel/tcg/tcg-runtime.h
View file

@ -28,6 +28,17 @@ DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env)
DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
#ifndef IN_HELPER_PROTO
/*
* Pass calls to memset directly to libc, without a thunk in qemu.
* Do not re-declare memset, especially since we fudge the type here;
* we assume sizeof(void *) == sizeof(size_t), which is true for
* all supported hosts.
*/
#define helper_memset memset
DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr)
#endif /* IN_HELPER_PROTO */
#ifdef CONFIG_SOFTMMU
DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,

3
qemu/include/exec/helper-proto.h
View file

@ -35,9 +35,12 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
dh_ctype(t7));
#define IN_HELPER_PROTO
#include "helper.h"
#include "tcg-runtime.h"
#undef IN_HELPER_PROTO
#undef DEF_HELPER_FLAGS_0
#undef DEF_HELPER_FLAGS_1
#undef DEF_HELPER_FLAGS_2

32
qemu/tcg/tcg-op-gvec.c
View file

@ -539,6 +539,9 @@ static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
in_c = dup_const(vece, in_c);
if (in_c == 0) {
oprsz = maxsz;
vece = MO_8;
} else if (in_c == dup_const(MO_8, in_c)) {
vece = MO_8;
}
}
@ -620,6 +623,35 @@ static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
/* Otherwise implement out of line. */
t_ptr = tcg_temp_new_ptr(s);
tcg_gen_addi_ptr(s, t_ptr, s->cpu_env, dofs);
/*
* This may be expand_clr for the tail of an operation, e.g.
* oprsz == 8 && maxsz == 64. The size of the clear is misaligned
* wrt simd_desc and will assert. Simply pass all replicated byte
* stores through to memset.
*/
if (oprsz == maxsz && vece == MO_8) {
TCGv_ptr t_size = tcg_const_ptr(s, oprsz);
TCGv_i32 t_val;
if (in_32) {
t_val = in_32;
} else if (in_64) {
t_val = tcg_temp_new_i32(s);
tcg_gen_extrl_i64_i32(s, t_val, in_64);
} else {
t_val = tcg_const_i32(s, in_c);
}
gen_helper_memset(s, t_ptr, t_ptr, t_val, t_size);
if (!in_32) {
tcg_temp_free_i32(s, t_val);
}
tcg_temp_free_ptr(s, t_size);
tcg_temp_free_ptr(s, t_ptr);
return;
}
t_desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, 0));
if (vece == MO_64) {