yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 05:05:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Fix SCR RES1 handling

Browse source 
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.

The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.

Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.

Backports 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5
This commit is contained in:
Mike Nawrocki 2021-03-04 18:15:15 -05:00 committed by Lioncash
parent 807d541e19
commit 4e482764e2
2 changed files with 19 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
qemu/target/arm/cpu.h
View file

@ -3884,6 +3884,11 @@ static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
} }
static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
}
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{ {
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;

14
qemu/target/arm/helper.c
View file

@ -1717,7 +1717,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
if (ri->state == ARM_CP_STATE_AA64) { if (ri->state == ARM_CP_STATE_AA64) {
if (arm_feature(env, ARM_FEATURE_AARCH64) &&
!cpu_isar_feature(aa64_aa32_el1, cpu)) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
}
valid_mask &= ~SCR_NET; valid_mask &= ~SCR_NET;
if (cpu_isar_feature(aa64_lor, cpu)) { if (cpu_isar_feature(aa64_lor, cpu)) {
@ -1762,6 +1765,15 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
raw_write(env, ri, value); raw_write(env, ri, value);
} }
static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
/*
* scr_write will set the RES1 bits on an AArch64-only CPU.
* The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
*/
scr_write(env, ri, 0);
}
static CPAccessResult access_aa64_tid2(CPUARMState *env, static CPAccessResult access_aa64_tid2(CPUARMState *env,
const ARMCPRegInfo *ri, const ARMCPRegInfo *ri,
bool isread) bool isread)
@ -5459,7 +5471,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.resetvalue = 0, .writefn = scr_write }, .resetfn = scr_reset, .writefn = scr_write },
{ .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL1_RW, .accessfn = access_trap_aa32s_el1, .access = PL1_RW, .accessfn = access_trap_aa32s_el1,