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target/riscv: Extend the SIP CSR to support virtulisation

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Backports commit a2e9f57d06279220b1834eca2494e52adae121b8 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:35:09 -04:00 committed by Lioncash
parent 1fd49ac6f0
commit 4e7aaee31a
1 changed files with 12 additions and 1 deletions
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13
qemu/target/riscv/csr.c
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@ -746,8 +746,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask) target_ulong new_value, target_ulong write_mask)
{ {
int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, int ret;
if (riscv_cpu_virt_enabled(env)) {
/* Shift the new values to line up with the VS bits */
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
(write_mask & sip_writable_mask) << 1 & env->mideleg);
ret &= vsip_writable_mask;
ret >>= 1;
} else {
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
write_mask & env->mideleg & sip_writable_mask); write_mask & env->mideleg & sip_writable_mask);
}
*ret_value &= env->mideleg; *ret_value &= env->mideleg;
return ret; return ret;
} }