mirror of
https://github.com/yuzu-emu/unicorn.git
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target/arm: Fix multiline comment syntax
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Backports commit 9a223097e44d5320f5e0546710263f22d11f12fc from qemu
This commit is contained in:
Philippe Mathieu-Daudé
Lioncash
parent
0a5152caf8
commit
4f71266524
File diff suppressed because it is too large
Load diff
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@ -96,7 +96,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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{
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uint32_t syn;
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/* ISV is only set for data aborts routed to EL2 and
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/*
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* ISV is only set for data aborts routed to EL2 and
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* never for stage-1 page table walks faulting on stage 2.
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*
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* Furthermore, ISV is only set for certain kinds of load/stores.
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@ -111,7 +112,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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syn = syn_data_abort_no_iss(same_el,
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ea, 0, s1ptw, is_write, fsc);
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} else {
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/* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
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/*
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* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
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* syndrome created at translation time.
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* Now we create the runtime syndrome with the remaining fields.
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*/
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@ -143,14 +145,16 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
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if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
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arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
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/* LPAE format fault status register : bottom 6 bits are
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/*
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* LPAE format fault status register : bottom 6 bits are
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* status code in the same form as needed for syndrome
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*/
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fsr = arm_fi_to_lfsc(fi);
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fsc = extract32(fsr, 0, 6);
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} else {
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fsr = arm_fi_to_sfsc(fi);
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/* Short format FSR : this fault will never actually be reported
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/*
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* Short format FSR : this fault will never actually be reported
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* to an EL that uses a syndrome register. Use a (currently)
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* reserved FSR code in case the constructed syndrome does leak
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* into the guest somehow.
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@ -193,7 +197,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
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}
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/* arm_cpu_do_transaction_failed: handle a memory system error response
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/*
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* arm_cpu_do_transaction_failed: handle a memory system error response
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* (eg "no device/memory present at address") by raising an external abort
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* exception
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*/
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@ -369,7 +374,8 @@ void HELPER(setend)(CPUARMState *env)
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env->uncached_cpsr ^= CPSR_E;
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}
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/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
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/*
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* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
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* The function returns the target EL (1-3) if the instruction is to be trapped;
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* otherwise it returns 0 indicating it is not trapped.
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*/
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@ -383,7 +389,8 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
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return 0;
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}
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/* If we are currently in EL0 then we need to check if SCTLR is set up for
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/*
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* If we are currently in EL0 then we need to check if SCTLR is set up for
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* WFx instructions being trapped to EL1. These trap bits don't exist in v7.
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*/
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if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
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@ -402,7 +409,8 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
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}
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}
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/* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
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/*
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* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
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* No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
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* bits will be zero indicating no trap.
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*/
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@ -430,7 +438,8 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
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int target_el = check_wfx_trap(env, false);
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if (cpu_has_work(cs)) {
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/* Don't bother to go into our "low power state" if
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/*
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* Don't bother to go into our "low power state" if
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* we would just wake up immediately.
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*/
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return;
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@ -449,7 +458,8 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
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void HELPER(wfe)(CPUARMState *env)
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{
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/* This is a hint instruction that is semantically different
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/*
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* This is a hint instruction that is semantically different
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* from YIELD even though we currently implement it identically.
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* Don't actually halt the CPU, just yield back to top
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* level loop. This is not going into a "low power state"
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@ -463,7 +473,8 @@ void HELPER(yield)(CPUARMState *env)
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{
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CPUState *cs = env_cpu(env);
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/* This is a non-trappable hint instruction that generally indicates
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/*
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* This is a non-trappable hint instruction that generally indicates
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* that the guest is currently busy-looping. Yield control back to the
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* top level loop so that a more deserving VCPU has a chance to run.
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*/
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@ -471,7 +482,8 @@ void HELPER(yield)(CPUARMState *env)
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cpu_loop_exit(cs);
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}
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/* Raise an internal-to-QEMU exception. This is limited to only
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/*
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* Raise an internal-to-QEMU exception. This is limited to only
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* those EXCP values which are special cases for QEMU to interrupt
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* execution and not to be used for exceptions which are passed to
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* the guest (those must all have syndrome information and thus should
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@ -493,14 +505,16 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
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raise_exception(env, excp, syndrome, target_el);
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}
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/* Raise an EXCP_BKPT with the specified syndrome register value,
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/*
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* Raise an EXCP_BKPT with the specified syndrome register value,
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* targeting the correct exception level for debug exceptions.
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*/
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void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
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{
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/* FSR will only be used if the debug target EL is AArch32. */
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env->exception.fsr = arm_debug_exception_fsr(env);
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/* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
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/*
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* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
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* values to the guest that it shouldn't be able to see at its
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* exception/security level.
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*/
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@ -525,7 +539,8 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
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cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
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/* Generated code has already stored the new PC value, but
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/*
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* Generated code has already stored the new PC value, but
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* without masking out its low bits, because which bits need
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* masking depends on whether we're returning to Thumb or ARM
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* state. Do the masking now.
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@ -579,7 +594,8 @@ void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
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/* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
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/*
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* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
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* Other UNPREDICTABLE and UNDEF cases were caught at translate time.
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*/
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raise_exception(env, EXCP_UDEF, syn_uncategorized(),
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@ -596,7 +612,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
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uint32_t regno)
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{
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/* Raise an exception if the requested access is one of the UNPREDICTABLE
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/*
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* Raise an exception if the requested access is one of the UNPREDICTABLE
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* cases; otherwise return. This broadly corresponds to the pseudocode
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* BankedRegisterAccessValid() and SPSRAccessValid(),
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* except that we have already handled some cases at translate time.
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@ -743,7 +760,8 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
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target_el = exception_target_el(env);
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break;
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case CP_ACCESS_TRAP_EL2:
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/* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
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/*
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* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
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* a bug in the access function.
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*/
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assert(!arm_is_secure(env) && arm_current_el(env) != 3);
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@ -766,7 +784,8 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
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break;
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case CP_ACCESS_TRAP_FP_EL2:
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target_el = 2;
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/* Since we are an implementation that takes exceptions on a trapped
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/*
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* Since we are an implementation that takes exceptions on a trapped
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* conditional insn only if the insn has passed its condition code
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* check, we take the IMPDEF choice to always report CV=1 COND=0xe
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* (which is also the required value for AArch64 traps).
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@ -821,7 +840,8 @@ void HELPER(pre_hvc)(CPUARMState *env)
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bool undef;
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if (arm_is_psci_call(cpu, EXCP_HVC)) {
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/* If PSCI is enabled and this looks like a valid PSCI call then
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/*
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* If PSCI is enabled and this looks like a valid PSCI call then
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* that overrides the architecturally mandated HVC behaviour.
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*/
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return;
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@ -837,7 +857,8 @@ void HELPER(pre_hvc)(CPUARMState *env)
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undef = env->cp15.hcr_el2 & HCR_HCD;
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}
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/* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
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/*
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* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
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* For ARMv8/AArch64, HVC is allowed in EL3.
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* Note that we've already trapped HVC from EL0 at translation
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* time.
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@ -889,7 +910,8 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
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* Conduit not SMC Undef insn Undef insn
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*/
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/* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
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/*
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* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
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* On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
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* extensions, SMD only applies to NS state.
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* On ARMv7 without the Virtualization extensions, the SMD bit
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@ -901,7 +923,8 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
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if (!arm_feature(env, ARM_FEATURE_EL3) &&
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cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
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/* If we have no EL3 then SMC always UNDEFs and can't be
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/*
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* If we have no EL3 then SMC always UNDEFs and can't be
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* trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
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* firmware within QEMU, and we want an EL2 guest to be able
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* to forbid its EL1 from making PSCI calls into QEMU's
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@ -914,7 +937,8 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
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}
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if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) {
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/* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
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/*
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* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
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* We also want an EL2 guest to be able to forbid its EL1 from
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* making PSCI calls into QEMU's "firmware" via HCR.TSC.
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* This handles all the "Trap to EL2" cases of the previous table.
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@ -922,7 +946,8 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
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raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
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}
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/* Catch the two remaining "Undef insn" cases of the previous table:
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/*
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* Catch the two remaining "Undef insn" cases of the previous table:
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* - PSCI conduit is SMC but we don't have a valid PCSI call,
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* - We don't have EL3 or SMD is set.
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*/
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@ -943,7 +968,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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int bt;
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uint32_t contextidr;
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/* Links to unimplemented or non-context aware breakpoints are
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/*
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* Links to unimplemented or non-context aware breakpoints are
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* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
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* as if linked to an UNKNOWN context-aware breakpoint (in which
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* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
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@ -962,7 +988,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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bt = extract64(bcr, 20, 4);
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/* We match the whole register even if this is AArch32 using the
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/*
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* We match the whole register even if this is AArch32 using the
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* short descriptor format (in which case it holds both PROCID and ASID),
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* since we don't implement the optional v7 context ID masking.
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*/
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@ -979,7 +1006,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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case 9: /* linked VMID match (reserved if no EL2) */
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case 11: /* linked context ID and VMID match (reserved if no EL2) */
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default:
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/* Links to Unlinked context breakpoints must generate no
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/*
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* Links to Unlinked context breakpoints must generate no
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* events; we choose to do the same for reserved values too.
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*/
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return false;
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@ -993,7 +1021,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
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CPUARMState *env = &cpu->env;
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uint64_t cr;
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int pac, hmc, ssc, wt, lbn;
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/* Note that for watchpoints the check is against the CPU security
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/*
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* Note that for watchpoints the check is against the CPU security
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* state, not the S/NS attribute on the offending data access.
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*/
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bool is_secure = arm_is_secure(env);
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@ -1022,7 +1051,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
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}
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cr = env->cp15.dbgbcr[n];
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}
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/* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
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/*
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* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
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* enabled and that the address and access type match; for breakpoints
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* we know the address matched; check the remaining fields, including
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* linked breakpoints. We rely on WCR and BCR having the same layout
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@ -1090,7 +1120,8 @@ static bool check_watchpoints(ARMCPU *cpu)
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CPUARMState *env = &cpu->env;
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int n;
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/* If watchpoints are disabled globally or we can't take debug
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/*
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* If watchpoints are disabled globally or we can't take debug
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* exceptions here then watchpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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@ -1111,7 +1142,8 @@ static bool check_breakpoints(ARMCPU *cpu)
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CPUARMState *env = &cpu->env;
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int n;
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/* If breakpoints are disabled globally or we can't take debug
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/*
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* If breakpoints are disabled globally or we can't take debug
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* exceptions here then breakpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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@ -1138,7 +1170,8 @@ void HELPER(check_breakpoints)(CPUARMState *env)
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bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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/* Called by core code when a CPU watchpoint fires; need to check if this
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/*
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* Called by core code when a CPU watchpoint fires; need to check if this
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* is also an architectural watchpoint match.
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*/
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ARMCPU *cpu = ARM_CPU(cs->uc, cs);
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@ -1151,7 +1184,8 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
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ARMCPU *cpu = ARM_CPU(cs->uc, cs);
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CPUARMState *env = &cpu->env;
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/* In BE32 system mode, target memory is stored byteswapped (on a
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/*
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* In BE32 system mode, target memory is stored byteswapped (on a
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* little-endian host system), and by the time we reach here (via an
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* opcode helper) the addresses of subword accesses have been adjusted
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* to account for that, which means that watchpoints will not match.
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@ -1170,7 +1204,8 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
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void arm_debug_excp_handler(CPUState *cs)
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{
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/* Called by core code when a watchpoint or breakpoint fires;
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/*
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* Called by core code when a watchpoint or breakpoint fires;
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* need to check which one and raise the appropriate exception.
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*/
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ARMCPU *cpu = ARM_CPU(cs->uc, cs);
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@ -1194,7 +1229,8 @@ void arm_debug_excp_handler(CPUState *cs)
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uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
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bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
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/* (1) GDB breakpoints should be handled first.
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/*
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* (1) GDB breakpoints should be handled first.
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* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
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* since singlestep is also done by generating a debug internal
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* exception.
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@ -1205,7 +1241,8 @@ void arm_debug_excp_handler(CPUState *cs)
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}
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env->exception.fsr = arm_debug_exception_fsr(env);
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/* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
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/*
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* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
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* values to the guest that it shouldn't be able to see at its
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* exception/security level.
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*/
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@ -1216,9 +1253,11 @@ void arm_debug_excp_handler(CPUState *cs)
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}
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}
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/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
|
||||
The only way to do that in TCG is a conditional branch, which clobbers
|
||||
all our temporaries. For now implement these as helper functions. */
|
||||
/*
|
||||
* ??? Flag setting arithmetic is awkward because we need to do comparisons.
|
||||
* The only way to do that in TCG is a conditional branch, which clobbers
|
||||
* all our temporaries. For now implement these as helper functions.
|
||||
*/
|
||||
|
||||
/* Similarly for variable shift instructions. */
|
||||
|
||||
|
|
|
|||
|
|
@ -25,9 +25,11 @@
|
|||
#include "internals.h"
|
||||
|
||||
|
||||
/* VFP support. We follow the convention used for VFP instructions:
|
||||
Single precision routines have a "s" suffix, double precision a
|
||||
"d" suffix. */
|
||||
/*
|
||||
* VFP support. We follow the convention used for VFP instructions:
|
||||
* Single precision routines have a "s" suffix, double precision a
|
||||
* "d" suffix.
|
||||
*/
|
||||
|
||||
/* Convert host exception flags to vfp form. */
|
||||
static inline int vfp_exceptbits_from_host(int host_bits)
|
||||
|
|
@ -170,7 +172,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
|
|||
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
|
||||
}
|
||||
|
||||
/* The exception flags are ORed together when we read fpscr so we
|
||||
/*
|
||||
* The exception flags are ORed together when we read fpscr so we
|
||||
* only need to preserve the current state in one of our
|
||||
* float_status values.
|
||||
*/
|
||||
|
|
@ -451,7 +454,8 @@ uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
|
|||
shift, fpst);
|
||||
}
|
||||
|
||||
/* Set the current fp rounding mode and return the old one.
|
||||
/*
|
||||
* Set the current fp rounding mode and return the old one.
|
||||
* The argument is a softfloat float_round_ value.
|
||||
*/
|
||||
uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
|
||||
|
|
@ -464,7 +468,8 @@ uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
|
|||
return prev_rmode;
|
||||
}
|
||||
|
||||
/* Set the current fp rounding mode in the standard fp status and return
|
||||
/*
|
||||
* Set the current fp rounding mode in the standard fp status and return
|
||||
* the old one. This is for NEON instructions that need to change the
|
||||
* rounding mode but wish to use the standard FPSCR values for everything
|
||||
* else. Always set the rounding mode back to the correct value after
|
||||
|
|
@ -484,7 +489,8 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
|
|||
/* Half precision conversions. */
|
||||
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
|
||||
{
|
||||
/* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
/*
|
||||
* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
* it would affect flushing input denormals.
|
||||
*/
|
||||
float_status *fpst = fpstp;
|
||||
|
|
@ -497,7 +503,8 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
|
|||
|
||||
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
|
||||
{
|
||||
/* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
/*
|
||||
* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
* it would affect flushing output denormals.
|
||||
*/
|
||||
float_status *fpst = fpstp;
|
||||
|
|
@ -510,7 +517,8 @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
|
|||
|
||||
float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
|
||||
{
|
||||
/* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
/*
|
||||
* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
* it would affect flushing input denormals.
|
||||
*/
|
||||
float_status *fpst = fpstp;
|
||||
|
|
@ -523,7 +531,8 @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
|
|||
|
||||
uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
|
||||
{
|
||||
/* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
/*
|
||||
* Squash FZ16 to 0 for the duration of conversion. In this case,
|
||||
* it would affect flushing output denormals.
|
||||
*/
|
||||
float_status *fpst = fpstp;
|
||||
|
|
@ -568,21 +577,25 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
|
|||
|
||||
/* NEON helpers. */
|
||||
|
||||
/* Constants 256 and 512 are used in some helpers; we avoid relying on
|
||||
* int->float conversions at run-time. */
|
||||
/*
|
||||
* Constants 256 and 512 are used in some helpers; we avoid relying on
|
||||
* int->float conversions at run-time.
|
||||
*/
|
||||
#define float64_256 make_float64(0x4070000000000000LL)
|
||||
#define float64_512 make_float64(0x4080000000000000LL)
|
||||
#define float16_maxnorm make_float16(0x7bff)
|
||||
#define float32_maxnorm make_float32(0x7f7fffff)
|
||||
#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
|
||||
|
||||
/* Reciprocal functions
|
||||
/*
|
||||
* Reciprocal functions
|
||||
*
|
||||
* The algorithm that must be used to calculate the estimate
|
||||
* is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
|
||||
*/
|
||||
|
||||
/* See RecipEstimate()
|
||||
/*
|
||||
* See RecipEstimate()
|
||||
*
|
||||
* input is a 9 bit fixed point number
|
||||
* input range 256 .. 511 for a number from 0.5 <= x < 1.0.
|
||||
|
|
@ -805,7 +818,8 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
|
|||
return make_float64(f64_val);
|
||||
}
|
||||
|
||||
/* The algorithm that must be used to calculate the estimate
|
||||
/*
|
||||
* The algorithm that must be used to calculate the estimate
|
||||
* is specified by the ARM ARM.
|
||||
*/
|
||||
|
||||
|
|
@ -887,8 +901,10 @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
|
|||
return float16_zero;
|
||||
}
|
||||
|
||||
/* Scale and normalize to a double-precision value between 0.25 and 1.0,
|
||||
* preserving the parity of the exponent. */
|
||||
/*
|
||||
* Scale and normalize to a double-precision value between 0.25 and 1.0,
|
||||
* preserving the parity of the exponent.
|
||||
*/
|
||||
|
||||
f64_frac = ((uint64_t) f16_frac) << (52 - 10);
|
||||
|
||||
|
|
@ -931,8 +947,10 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
|
|||
return float32_zero;
|
||||
}
|
||||
|
||||
/* Scale and normalize to a double-precision value between 0.25 and 1.0,
|
||||
* preserving the parity of the exponent. */
|
||||
/*
|
||||
* Scale and normalize to a double-precision value between 0.25 and 1.0,
|
||||
* preserving the parity of the exponent.
|
||||
*/
|
||||
|
||||
f64_frac = ((uint64_t) f32_frac) << 29;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue