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target/arm: Implement PMOVSSET

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Add an array for PMOVSSET so we only define it for v7ve+ platforms

Backports commit 327dd5108bb3b66bb5102b659e83a4348a005f5e from qemu
This commit is contained in:
Aaron Lindsay 2019-01-22 17:24:49 -05:00 committed by Lioncash
parent d6d1d49cdd
commit 4ff0389d2d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 21 additions and 0 deletions
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21
qemu/target/arm/helper.c
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@ -1206,6 +1206,13 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.c9_pmovsr &= ~value;
}
static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
value &= pmu_counter_mask(env);
env->cp15.c9_pmovsr |= value;
}
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@ -1533,6 +1540,17 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
REGINFO_SENTINEL
};
static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
/* PMOVSSET is not implemented in v7 before v7ve */
{ "PMOVSSET", 15,9,14, 0,0,3, 0, ARM_CP_ALIAS, PL0_RW, 0,
NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmovsr), {0, 0},
pmreg_access, NULL, pmovsset_write, NULL, raw_write },
{ "PMOVSSET_EL0", 0,9,14, 3,3,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL0_RW, 0,
NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
pmreg_access, NULL, pmovsset_write, NULL, raw_write },
REGINFO_SENTINEL
};
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@ -4730,6 +4748,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
!arm_feature(env, ARM_FEATURE_PMSA)) {
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7VE)) {
define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle