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target-mips: Add delayed branch state to insn_start

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Backports commit c20d594e45bc8c4b21be1a7637cba0f279f72879 from qemu
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Richard Henderson 2018-02-16 00:34:25 -05:00 committed by Lioncash
parent 96e0535c76
commit 500e116581
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 4 additions and 2 deletions
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1
qemu/target-mips/cpu.h
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@ -131,6 +131,7 @@ struct CPUMIPSFPUContext {
}; };
#define NB_MMU_MODES 3 #define NB_MMU_MODES 3
#define TARGET_INSN_START_EXTRA_WORDS 2
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext { struct CPUMIPSMVPContext {

3
qemu/target-mips/translate.c
View file

@ -19722,6 +19722,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
ctx.CP0_Config1 = env->CP0_Config1; ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb; ctx.tb = tb;
ctx.bstate = BS_NONE; ctx.bstate = BS_NONE;
ctx.btarget = 0;
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3; ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
@ -19798,7 +19799,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
tcg_ctx->gen_opc_instr_start[lj] = 1; tcg_ctx->gen_opc_instr_start[lj] = 1;
tcg_ctx->gen_opc_icount[lj] = num_insns; tcg_ctx->gen_opc_icount[lj] = num_insns;
} }
tcg_gen_insn_start(tcg_ctx, ctx.pc); tcg_gen_insn_start(tcg_ctx, ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++; num_insns++;
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {

2
qemu/tcg/tcg-op.h
View file

@ -735,7 +735,7 @@ static inline void tcg_gen_insn_start(TCGContext *tcg_ctx, target_ulong pc, targ
tcg_gen_op3(tcg_ctx, INDEX_op_insn_start, pc, a1, a2); tcg_gen_op3(tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
} }
# else # else
static inline void tcg_gen_insn_start(TCGContect *tcg_ctx, target_ulong pc, target_ulong a1, static inline void tcg_gen_insn_start(TCGContext *tcg_ctx, target_ulong pc, target_ulong a1,
target_ulong a2) target_ulong a2)
{ {
tcg_gen_op6(tcg_ctx, INDEX_op_insn_start, tcg_gen_op6(tcg_ctx, INDEX_op_insn_start,