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target-mips: Add delayed branch state to insn_start
Backports commit c20d594e45bc8c4b21be1a7637cba0f279f72879 from qemu
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96e0535c76
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500e116581
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@ -131,6 +131,7 @@ struct CPUMIPSFPUContext {
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};
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#define NB_MMU_MODES 3
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#define TARGET_INSN_START_EXTRA_WORDS 2
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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struct CPUMIPSMVPContext {
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@ -19722,6 +19722,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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ctx.CP0_Config1 = env->CP0_Config1;
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ctx.tb = tb;
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ctx.bstate = BS_NONE;
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ctx.btarget = 0;
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ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
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ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
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ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
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@ -19798,7 +19799,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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tcg_ctx->gen_opc_instr_start[lj] = 1;
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tcg_ctx->gen_opc_icount[lj] = num_insns;
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}
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tcg_gen_insn_start(tcg_ctx, ctx.pc);
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tcg_gen_insn_start(tcg_ctx, ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
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num_insns++;
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//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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@ -735,7 +735,7 @@ static inline void tcg_gen_insn_start(TCGContext *tcg_ctx, target_ulong pc, targ
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tcg_gen_op3(tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
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}
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# else
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static inline void tcg_gen_insn_start(TCGContect *tcg_ctx, target_ulong pc, target_ulong a1,
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static inline void tcg_gen_insn_start(TCGContext *tcg_ctx, target_ulong pc, target_ulong a1,
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target_ulong a2)
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{
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tcg_gen_op6(tcg_ctx, INDEX_op_insn_start,
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