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target/arm: Convert Neon 2-reg-misc VREV64 to decodetree

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Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.

Backports commit 353d2b85058711a5e44c2dc63eb5b620db50a602 from qemu
This commit is contained in:
Peter Maydell 2021-02-25 12:06:16 -05:00 committed by Lioncash
parent e1f49dc888
commit 505923e676
3 changed files with 65 additions and 22 deletions
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12
qemu/target/arm/neon-dp.decode
View file

@ -429,6 +429,18 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
vm=%vm_dp vd=%vd_dp size=1
VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
vm=%vm_dp vd=%vd_dp size=2
##################################################################
# 2-reg-misc grouping:
# 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
##################################################################
&2misc vd vm q size
@2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
&2misc vm=%vm_dp vd=%vd_dp
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
]
# Subgroup for size != 0b11

51
qemu/target/arm/translate-neon.inc.c
View file

@ -3007,3 +3007,54 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
a->q ? 16 : 8, a->q ? 16 : 8);
return true;
}
static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
{
int pass, half;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vm) & 0x10)) {
return false;
}
if ((a->vd | a->vm) & a->q) {
return false;
}
if (a->size == 3) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
TCGv_i32 tmp[2];
for (half = 0; half < 2; half++) {
tmp[half] = neon_load_reg(s, a->vm, pass * 2 + half);
switch (a->size) {
case 0:
tcg_gen_bswap32_i32(tcg_ctx, tmp[half], tmp[half]);
break;
case 1:
gen_swap_half(s, tmp[half]);
break;
case 2:
break;
default:
g_assert_not_reached();
}
}
neon_store_reg(s, a->vd, pass * 2, tmp[1]);
neon_store_reg(s, a->vd, pass * 2 + 1, tmp[0]);
}
return true;
}

24
qemu/target/arm/translate.c
View file

@ -5205,28 +5205,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
switch (op) {
case NEON_2RM_VREV64:
for (pass = 0; pass < (q ? 2 : 1); pass++) {
tmp = neon_load_reg(s, rm, pass * 2);
tmp2 = neon_load_reg(s, rm, pass * 2 + 1);
switch (size) {
case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp, tmp); break;
case 1: gen_swap_half(s, tmp); break;
case 2: /* no-op */ break;
default: abort();
}
neon_store_reg(s, rd, pass * 2 + 1, tmp);
if (size == 2) {
neon_store_reg(s, rd, pass * 2, tmp2);
} else {
switch (size) {
case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp2, tmp2); break;
case 1: gen_swap_half(s, tmp2); break;
default: abort();
}
neon_store_reg(s, rd, pass * 2, tmp2);
}
}
break;
/* handled by decodetree */
return 1;
case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
for (pass = 0; pass < q + 1; pass++) {