tcg: Make store_dummy a TCGv

Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
This commit is contained in:
Lioncash 2018-02-21 00:24:37 -05:00
parent 53f66f4762
commit 50b871f523
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 9 deletions

View file

@ -91,10 +91,7 @@ void m68k_tcg_init(struct uc_struct *uc)
}
tcg_ctx->NULL_QREG = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, -4, "NULL");
if (!uc->init_tcg)
tcg_ctx->store_dummy = g_malloc0(sizeof(TCGv));
*((TCGv *)tcg_ctx->store_dummy) = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, -8, "NULL");
tcg_ctx->store_dummy = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, -8, "NULL");
uc->init_tcg = true;
}
@ -232,7 +229,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
if (what == EA_STORE) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_store(s, opsize, addr, val);
return *(TCGv *)tcg_ctx->store_dummy;
return tcg_ctx->store_dummy;
} else {
return gen_load(s, opsize, addr, what == EA_LOADS);
}
@ -576,7 +573,7 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
reg = DREG(insn, 0);
if (what == EA_STORE) {
gen_partset_reg(s, opsize, reg, val);
return *(TCGv *)tcg_ctx->store_dummy;
return tcg_ctx->store_dummy;
} else {
return gen_extend(s, reg, opsize, what == EA_LOADS);
}
@ -584,7 +581,7 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
reg = AREG(insn, 0);
if (what == EA_STORE) {
tcg_gen_mov_i32(tcg_ctx, reg, val);
return *(TCGv *)tcg_ctx->store_dummy;
return tcg_ctx->store_dummy;
} else {
return gen_extend(s, reg, opsize, what == EA_LOADS);
}

View file

@ -24,7 +24,6 @@ void m68k_release(void* ctx)
release_common(ctx);
g_free(tcg_ctx->tb_ctx.tbs);
g_free(tcg_ctx->store_dummy);
}
void m68k_reg_reset(struct uc_struct *uc)

View file

@ -792,7 +792,7 @@ struct TCGContext {
TCGv NULL_QREG;
void *opcode_table[65536];
/* Used to distinguish stores from bad addressing modes. */
void *store_dummy;
TCGv store_dummy;
/* qemu/target-arm/translate.c */
TCGv_i64 cpu_V0, cpu_V1, cpu_M0;