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target/arm: Introduce aarch64_pstate_valid_mask
Use this along the exception return path, where we previously accepted any values Backports commit 140845111809cd6fd57ccde93867b48cc56ffc74 from qemu
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@ -1030,6 +1030,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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cur_el, new_el, env->regs[15]);
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} else {
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env->aarch64 = 1;
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spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
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pstate_write(env, spsr);
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if (!arm_singlestep_active(env)) {
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env->pstate &= ~PSTATE_SS;
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@ -1087,6 +1087,18 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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return valid;
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}
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static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
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{
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uint32_t valid;
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valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
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if (isar_feature_aa64_bti(id)) {
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valid |= PSTATE_BTYPE;
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}
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return valid;
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}
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/*
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* Parameters of a given virtual address, as extracted from the
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* translation control register (TCR) for a given regime.
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