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target/arm: Introduce aarch64_pstate_valid_mask

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Use this along the exception return path, where we previously
accepted any values

Backports commit 140845111809cd6fd57ccde93867b48cc56ffc74 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:25:33 -04:00 committed by Lioncash
parent b6b69d7ac5
commit 50bb867a6f
2 changed files with 13 additions and 0 deletions
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1
qemu/target/arm/helper-a64.c
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@ -1030,6 +1030,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
cur_el, new_el, env->regs[15]); cur_el, new_el, env->regs[15]);
} else { } else {
env->aarch64 = 1; env->aarch64 = 1;
spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
pstate_write(env, spsr); pstate_write(env, spsr);
if (!arm_singlestep_active(env)) { if (!arm_singlestep_active(env)) {
env->pstate &= ~PSTATE_SS; env->pstate &= ~PSTATE_SS;

12
qemu/target/arm/internals.h
View file

@ -1087,6 +1087,18 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
return valid; return valid;
} }
static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
{
uint32_t valid;
valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
if (isar_feature_aa64_bti(id)) {
valid |= PSTATE_BTYPE;
}
return valid;
}
/* /*
* Parameters of a given virtual address, as extracted from the * Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime. * translation control register (TCR) for a given regime.