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target/arm: [tcg,a64] Port to init_disas_context
Incrementally paves the way towards using the generic instruction translation loop. Backports commit 5c03990665aa9095e4d2734c8ca0f936a8e8f000 from qemu
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5e5c722359
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@ -11444,24 +11444,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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free_tmp_a64(s);
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}
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void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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TranslationBlock *tb)
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static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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CPUState *cpu, int max_insns)
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{
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CPUARMState *env = cs->env_ptr;
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ARMCPU *cpu = arm_env_get_cpu(env);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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target_ulong next_page_start;
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int max_insns;
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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bool block_full = false;
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dc->base.tb = tb;
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dc->base.pc_first = dc->base.tb->pc;
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dc->base.pc_next = dc->base.pc_first;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.num_insns = 0;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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CPUARMState *env = cpu->env_ptr;
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ARMCPU *arm_cpu = arm_env_get_cpu(env);
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// Unicorn: Store uc context
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dc->uc = env->uc;
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dc->pc = dc->base.pc_first;
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@ -11488,7 +11478,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
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dc->vec_len = 0;
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dc->vec_stride = 0;
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dc->cp_regs = cpu->cp_regs;
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dc->cp_regs = arm_cpu->cp_regs;
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dc->features = env->features;
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/* Single step state. The code-generation logic here is:
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@ -11513,6 +11503,26 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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init_tmp_a64_array(dc);
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return max_insns;
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}
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void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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TranslationBlock *tb)
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{
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CPUARMState *env = cs->env_ptr;
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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target_ulong next_page_start;
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int max_insns;
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bool block_full = false;
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dc->base.tb = tb;
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dc->base.pc_first = dc->base.tb->pc;
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dc->base.pc_next = dc->base.pc_first;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.num_insns = 0;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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@ -11521,6 +11531,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
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tcg_clear_temp_count();
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